From patchwork Sat May 5 10:53:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 135077 Delivered-To: patch@linaro.org Received: by 10.46.151.6 with SMTP id r6csp1089455lji; Sat, 5 May 2018 03:58:46 -0700 (PDT) X-Google-Smtp-Source: AB8JxZoQmXuHuWFHYEubGsqVcdIajkzVwnFfSrWn35CfHSyOBeQG8bSCIj9nc+prZJCl/7FEwcHx X-Received: by 2002:a50:fc0c:: with SMTP id i12-v6mr40093519edr.74.1525517926132; Sat, 05 May 2018 03:58:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1525517926; cv=none; d=google.com; s=arc-20160816; b=nBI7PMZeiH8AJuWtE+xA7d3/2d0PaLdiGp5MOMxA+XHcps3jg11FYmmDyaJf4X1ol7 hOgyJee5lcXx3QfyzFRz6VdPI/BQzR/ORpua8lwG0SKdbDCIfpUkSux0OsfP1vcP7fzW TWqZntdWi/6mm62hH7JQW9OofTEudSFiWFmTHSojEEbV4XzXAqEJaP3bZGbDEewBcPIQ 6ERgidYMWVB5RSs6W1LPkr1vzyscg+64xIOST8xy95iazhQmz3x8i4gIGudVlp9aIATv uEZmAbtXGb1mAz9vp/memxMyxa5gcnCoeN610NptSBfPfoJUBoMQfc+OfiImXHbWbe21 tiOA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:dkim-filter:arc-authentication-results; bh=6jiutLslzaglAGv8Is2kkqbUVGzyF0OaeY4UM/qdWyg=; b=RdeTcjufmv2t54PyUxAE78SnQG5edCRtwa3s+KBlfXkRmYnt7ncJD//RFoJgCoIgFK ibvEradyL7325TSPpua37SXE6fi9dYJdOTuq0ZsYaDt/fTaZTRDMgYQLbGrYumI0Tlit zSUu6JP6S2eCYBHLKbFoOd+XccJMSDEORo8zlF4prBeZo0yB8IiNQiQJ7Jnem2fL+ERh mmHbyxDyzi4bf7sPqkxQ6BM4krC1eMQ6W7mF4ADucOSRDB5eyi3IHRRvxejRJnVPOiWH //1dI1McbVLt93TIreCTb6z0Liv4V/wz79t9uPMzHA0P/ePBrbAf1iGICvUbrZHfpCP+ wmLA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=bK/9pt1u; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id x40-v6si641852edx.299.2018.05.05.03.58.45; Sat, 05 May 2018 03:58:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=bK/9pt1u; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id B304AC21FC7; Sat, 5 May 2018 10:55:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 19FD3C21FB1; Sat, 5 May 2018 10:54:20 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 1CCB3C21F1C; Sat, 5 May 2018 10:54:15 +0000 (UTC) Received: from conuserg-08.nifty.com (conuserg-08.nifty.com [210.131.2.75]) by lists.denx.de (Postfix) with ESMTPS id DB348C21F41 for ; Sat, 5 May 2018 10:54:14 +0000 (UTC) Received: from grover.sesame (FL1-125-199-20-195.osk.mesh.ad.jp [125.199.20.195]) (authenticated) by conuserg-08.nifty.com with ESMTP id w45As4Ev023712; Sat, 5 May 2018 19:54:07 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-08.nifty.com w45As4Ev023712 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1525517647; bh=trk+Er6bVJ+Q4WpXnw0gToksizvrhXEYSUX/iXtnv0g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bK/9pt1u07UG1BYTevyRtg09yF0iR3e4luVfDGb8xh1aWI8J3vZrr9upPNc/YQd9D +/TEpUFNx+bvoILdk1Sf3IBVXzVEjlSMJogjuQY28lCQMEq1xa3wSuAP3sWJiNwAvZ YyMrNX65B83RsL+fyA1xSi69xH06FEDSIPZwNdQ7kb4iaXAF1q7ZQTqJm7omjkaDcB MTHcdr3OvGpaievO2JvtXIGjE2t7KlQBklNfDtamDJ47u1pH45IxQW7b8YKlcGrPcD xEdA/APFcI/HcXHVCgSgv02aC93Q9NnyEiRMuOsmpuoMawAjtWSDXRR2eELXvqHGtF 0Cm9E2Kf5FTUw== X-Nifty-SrcIP: [125.199.20.195] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Sat, 5 May 2018 19:53:55 +0900 Message-Id: <1525517637-17603-6-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1525517637-17603-1-git-send-email-yamada.masahiro@socionext.com> References: <1525517637-17603-1-git-send-email-yamada.masahiro@socionext.com> Subject: [U-Boot] [PATCH 5/7] pinctrl: uniphier: support drive-strength configuration X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This allows our DT to specify drive-strength property. Signed-off-by: Masahiro Yamada --- drivers/pinctrl/uniphier/pinctrl-uniphier-core.c | 101 +++++++++++++++++++++++ drivers/pinctrl/uniphier/pinctrl-uniphier.h | 44 ++++++++-- 2 files changed, 140 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c index 03103b3..39b5366 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c @@ -17,6 +17,9 @@ #define UNIPHIER_PINCTRL_PINMUX_BASE 0x1000 #define UNIPHIER_PINCTRL_LOAD_PINMUX 0x1700 +#define UNIPHIER_PINCTRL_DRVCTRL_BASE 0x1800 +#define UNIPHIER_PINCTRL_DRV2CTRL_BASE 0x1900 +#define UNIPHIER_PINCTRL_DRV3CTRL_BASE 0x1980 #define UNIPHIER_PINCTRL_PUPDCTRL_BASE 0x1a00 #define UNIPHIER_PINCTRL_IECTRL 0x1d00 @@ -142,10 +145,25 @@ static const struct pinconf_param uniphier_pinconf_params[] = { { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 }, { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 }, { "bias-pull-pin-default", PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, 1 }, + { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 }, { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 }, }; +static const struct uniphier_pinctrl_pin * +uniphier_pinctrl_pin_get(struct uniphier_pinctrl_priv *priv, unsigned int pin) +{ + const struct uniphier_pinctrl_pin *pins = priv->socdata->pins; + int pins_count = priv->socdata->pins_count; + int i; + + for (i = 0; i < pins_count; i++) + if (pins[i].number == pin) + return &pins[i]; + + return NULL; +} + static int uniphier_pinconf_bias_set(struct udevice *dev, unsigned int pin, unsigned int param, unsigned int arg) { @@ -186,6 +204,86 @@ static int uniphier_pinconf_bias_set(struct udevice *dev, unsigned int pin, return 0; } +static const unsigned int uniphier_pinconf_drv_strengths_1bit[] = { + 4, 8, +}; + +static const unsigned int uniphier_pinconf_drv_strengths_2bit[] = { + 8, 12, 16, 20, +}; + +static const unsigned int uniphier_pinconf_drv_strengths_3bit[] = { + 4, 5, 7, 9, 11, 12, 14, 16, +}; + +static int uniphier_pinconf_drive_set(struct udevice *dev, unsigned int pin, + unsigned int strength) +{ + struct uniphier_pinctrl_priv *priv = dev_get_priv(dev); + const struct uniphier_pinctrl_pin *desc; + const unsigned int *strengths; + unsigned int base, stride, width, drvctrl, reg, shift; + u32 val, mask, tmp; + + desc = uniphier_pinctrl_pin_get(priv, pin); + if (WARN_ON(!desc)) + return -EINVAL; + + switch (uniphier_pin_get_drv_type(desc->data)) { + case UNIPHIER_PIN_DRV_1BIT: + strengths = uniphier_pinconf_drv_strengths_1bit; + base = UNIPHIER_PINCTRL_DRVCTRL_BASE; + stride = 1; + width = 1; + break; + case UNIPHIER_PIN_DRV_2BIT: + strengths = uniphier_pinconf_drv_strengths_2bit; + base = UNIPHIER_PINCTRL_DRV2CTRL_BASE; + stride = 2; + width = 2; + break; + case UNIPHIER_PIN_DRV_3BIT: + strengths = uniphier_pinconf_drv_strengths_3bit; + base = UNIPHIER_PINCTRL_DRV3CTRL_BASE; + stride = 4; + width = 3; + break; + default: + /* drive strength control is not supported for this pin */ + return -EINVAL; + } + + drvctrl = uniphier_pin_get_drvctrl(desc->data); + drvctrl *= stride; + + reg = base + drvctrl / 32 * 4; + shift = drvctrl % 32; + mask = (1U << width) - 1; + + for (val = 0; val <= mask; val++) { + if (strengths[val] > strength) + break; + } + + if (val == 0) { + dev_err(dev, "unsupported drive strength %u mA for pin %s\n", + strength, desc->name); + return -EINVAL; + } + + if (!mask) + return 0; + + val--; + + tmp = readl(priv->base + reg); + tmp &= ~(mask << shift); + tmp |= (mask & val) << shift; + writel(tmp, priv->base + reg); + + return 0; +} + static int uniphier_pinconf_set(struct udevice *dev, unsigned int pin, unsigned int param, unsigned int arg) { @@ -198,6 +296,9 @@ static int uniphier_pinconf_set(struct udevice *dev, unsigned int pin, case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: ret = uniphier_pinconf_bias_set(dev, pin, param, arg); break; + case PIN_CONFIG_DRIVE_STRENGTH: + ret = uniphier_pinconf_drive_set(dev, pin, arg); + break; case PIN_CONFIG_INPUT_ENABLE: ret = uniphier_pinconf_input_enable(dev, pin, arg); break; diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier.h b/drivers/pinctrl/uniphier/pinctrl-uniphier.h index 8884b08..3f47693 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier.h +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier.h @@ -13,11 +13,44 @@ #include #include -#define UNIPHIER_PIN_ATTR_PACKED(iectrl) (iectrl) +/* drive strength control register number */ +#define UNIPHIER_PIN_DRVCTRL_SHIFT 0 +#define UNIPHIER_PIN_DRVCTRL_BITS 9 +#define UNIPHIER_PIN_DRVCTRL_MASK ((1U << (UNIPHIER_PIN_DRVCTRL_BITS)) \ + - 1) + +/* drive control type */ +#define UNIPHIER_PIN_DRV_TYPE_SHIFT ((UNIPHIER_PIN_DRVCTRL_SHIFT) + \ + (UNIPHIER_PIN_DRVCTRL_BITS)) +#define UNIPHIER_PIN_DRV_TYPE_BITS 2 +#define UNIPHIER_PIN_DRV_TYPE_MASK ((1U << (UNIPHIER_PIN_DRV_TYPE_BITS)) \ + - 1) + +/* drive control type */ +enum uniphier_pin_drv_type { + UNIPHIER_PIN_DRV_1BIT, /* 2 level control: 4/8 mA */ + UNIPHIER_PIN_DRV_2BIT, /* 4 level control: 8/12/16/20 mA */ + UNIPHIER_PIN_DRV_3BIT, /* 8 level control: 4/5/7/9/11/12/14/16 mA */ +}; + +#define UNIPHIER_PIN_DRVCTRL(x) \ + (((x) & (UNIPHIER_PIN_DRVCTRL_MASK)) << (UNIPHIER_PIN_DRVCTRL_SHIFT)) +#define UNIPHIER_PIN_DRV_TYPE(x) \ + (((x) & (UNIPHIER_PIN_DRV_TYPE_MASK)) << (UNIPHIER_PIN_DRV_TYPE_SHIFT)) + +#define UNIPHIER_PIN_ATTR_PACKED(drvctrl, drv_type) \ + UNIPHIER_PIN_DRVCTRL(drvctrl) | \ + UNIPHIER_PIN_DRV_TYPE(drv_type) + +static inline unsigned int uniphier_pin_get_drvctrl(unsigned int data) +{ + return (data >> UNIPHIER_PIN_DRVCTRL_SHIFT) & UNIPHIER_PIN_DRVCTRL_MASK; +} -static inline unsigned int uniphier_pin_get_iectrl(unsigned long data) +static inline unsigned int uniphier_pin_get_drv_type(unsigned int data) { - return data; + return (data >> UNIPHIER_PIN_DRV_TYPE_SHIFT) & + UNIPHIER_PIN_DRV_TYPE_MASK; } /** @@ -74,10 +107,11 @@ struct uniphier_pinctrl_socdata { #define UNIPHIER_PINCTRL_CAPS_MUX_4BIT BIT(0) }; -#define UNIPHIER_PINCTRL_PIN(a, b) \ +#define UNIPHIER_PINCTRL_PIN(a, b, c, d) \ { \ .number = a, \ - .data = UNIPHIER_PIN_ATTR_PACKED(b), \ + .name = b, \ + .data = UNIPHIER_PIN_ATTR_PACKED(c, d), \ } #define __UNIPHIER_PINCTRL_GROUP(grp) \