From patchwork Thu Apr 5 18:46:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 132885 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp6623888ljb; Thu, 5 Apr 2018 11:46:14 -0700 (PDT) X-Google-Smtp-Source: AIpwx48k+IxWQOKpzGau8kGCcDFEgCjHDirRYcnSbbnQ9L+0TLv3+EBHx2UVYVJgdGTOO9WK6bw2 X-Received: by 10.80.211.3 with SMTP id g3mr3961304edh.15.1522953974213; Thu, 05 Apr 2018 11:46:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1522953974; cv=none; d=google.com; s=arc-20160816; b=HSM2HIjS5AABo+GUpqc1cAR0JrGJhIhk+FFbaA3HOywX+iWZ5N5jCCaUco4qwq221+ Ko7FT7EHi5O+4Uv4aPy2LUQLu8axFhoPgEteFw94e8wr4mkVNVfrbkaS0eKjVqf3ArEc 6DmZkbF81F444ytiwFHF1mh1e4T0N2upVBN5RLH3pTM0OWcMW2ADRAti4aqWMpNaZTpV 7UXqJTe3MCoEnQgEae1YmeYCWlzFaTP6OykwAQwCjn1g7jf8fmAxdsFMC5xCq7jdQ2gi DlaWs0N+lBfOFayEP9YG4vKu/tHiz2hhTqij34jOhprQyujQqZAFBF9pmJiVEZ9WBm62 zUWQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=VI8Js5jqjrNPf3bHPr41oyScnNAe9adfjqDilrNxo/Q=; b=sS9LcN/0m+ooYliGt7SHH7v5vTUQodgzOp2m5/k1lgmpPkm5cVFHRA9lvN8u8jw7pR 1TpqHipvr5CcvUqR3RwcYTo8pU8i4QbZc3hZlY/MY02pDDd0OcSKD3/E1obiQX+z8p8q Ij/WVDlqqH5LEay0xBjF1SvcNZDfizkaZ3yrgF56PFLYbC/rXw1WBgG8pibrmK1UBiSm mUUiexN7O5iH6nYZGcPCWu2PCO/RqR+WXdSBzp5JCT0gSjV/r/Bcvfy5TCnQf8ERJpxx 1R++YjeQz2t4EgWutvLFLZtMPjuoi8RSltS0drFaDAQs9zuuuO0nFHs8WOVtYzay7d2o wvWA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=kEIBrlfu; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id l41si1644931edd.268.2018.04.05.11.46.13; Thu, 05 Apr 2018 11:46:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=kEIBrlfu; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.denx.de (Postfix, from userid 105) id B86EAC21DB3; Thu, 5 Apr 2018 18:46:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id BDA10C21C2F; Thu, 5 Apr 2018 18:46:10 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 8C154C21C51; Thu, 5 Apr 2018 18:46:09 +0000 (UTC) Received: from mail-wm0-f68.google.com (mail-wm0-f68.google.com [74.125.82.68]) by lists.denx.de (Postfix) with ESMTPS id 1D864C21C29 for ; Thu, 5 Apr 2018 18:46:09 +0000 (UTC) Received: by mail-wm0-f68.google.com with SMTP id g8so8195545wmd.2 for ; Thu, 05 Apr 2018 11:46:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=ksQo65sQRN7XV1DkQm+q0RkkqsNKULYyWsj3GsILoKg=; b=kEIBrlfu+Ctzer8jMbmHwR9+ma61VIkXLcunnGh8p/Kj5iPUwPbmcga5VY7HgYW0cb hjvos9SMr+7XidPsedZJZmEYvkgjHWqItIdpNWjiEFez28RsPrht3KmrTVnoCZ6NxLzj CXOQ9AnclAwGTuw8SrLuK42IbPLXmtkIlCh2k= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=ksQo65sQRN7XV1DkQm+q0RkkqsNKULYyWsj3GsILoKg=; b=SFH4d1D9nns/rJconcIopGJCBx82B+35ce58rO4x7pkULARuH5t4gQx5EzX5X4ZVqK lBierq0wVUJeRIjnyx3TX1Pu/P0YDcS1oGOlMwuHoNcAZ5ZdrHzt/Ki3yzJks657U3P1 4Tu3ogMOP+dRe6czkXzLqNaV2W2BTRvFh/XQGSfXowpctsM3uw/j/xl30CQS0r7rJ2Gb QkYz+D1WAM57w9fVRHT+NTSO+WO8Cu2Q3dZxX5Foq+GbOvFR5hbpIeIaRMnVw2PgFSwE h4Ml+7XJCLNOCWGIrgKhHG/cF2vOKLMaG4tfEZSNBSyxFWFUhCIwAZr31jgL/qr8oRpq aUxA== X-Gm-Message-State: ALQs6tDz6TdCxd7D2b6UmtUPcKcQtDi26Bn6dF7vUYwLxhjJ2eNO4CgJ QcLjOMtWakJpIDhvbD7F+ftGaajlR4I= X-Received: by 10.80.134.99 with SMTP id 32mr3875843edt.229.1522953968416; Thu, 05 Apr 2018 11:46:08 -0700 (PDT) Received: from localhost.localdomain ([109.255.42.2]) by smtp.gmail.com with ESMTPSA id q7sm5230188edl.92.2018.04.05.11.46.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 05 Apr 2018 11:46:07 -0700 (PDT) From: Bryan O'Donoghue To: u-boot@lists.denx.de, fabio.estevam@nxp.com Date: Thu, 5 Apr 2018 19:46:06 +0100 Message-Id: <1522953966-14156-1-git-send-email-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.7.4 Cc: breno.lima@nxp.com Subject: [U-Boot] [PATCH] imx: mx7: snvs: Add an SNVS init routine X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Working with HAB on the i.MX7 we've encountered a case where a board that successfully authenticates u-boot when booting Linux via OPTEE subsequently fails to properly bring up the RTC. The RTC registers live in the low-power block of the Secure Non-Volatile Storage (SNVS) block. The root cause of the error has been traced to the HAB handing off the SNVS-RTC in a state where HPCOMR::NPSWA_EN = 0 in other words where the Non-Privileged Software Access Enable bit is zero. In ordinary circumstances this is OK since we typically do not run in TZ mode, however when we boot via HAB and enablng TrustZone, it is required to set HPCOMR::NPSWA_EN = 1 in order for the upstream Linux driver to have sufficient permissions to manipulate the SNVS-LP block. On our reference board it is the difference between Linux doing this: root@imx7s-warp-mbl:~# dmesg | grep rtc snvs_rtc_enable read 0x00000000 from SNVS_LPLR @ 0x00000034 snvs_rtc_enable read 0x00000021 from SNVS_LPCR @ 0x00000038 snvs_rtc_enable read 0x00000000 from SNVS_HPLR @ 0x00000000 snvs_rtc_enable read 0x80002100 from SNVS_HPCOMR @ 0x00000004 snvs_rtc 30370000.snvs:snvs-rtc-lp: rtc core: registered 30370000.snvs:snvs-rtc-lp as rtc0 snvs_rtc 30370000.snvs:snvs-rtc-lp: setting system clock to2018-04-01 00:51:04 UTC (1522543864) and doing this: root@imx7s-warp-mbl:~# dmesg | grep rtc snvs_rtc_enable read 0x00000000 from SNVS_LPLR @ 0x00000034 snvs_rtc_enable read 0x00000020 from SNVS_LPCR @ 0x00000038 snvs_rtc_enable read 0x00000001 from SNVS_HPLR @ 0x00000000 snvs_rtc_enable read 0x00002020 from SNVS_HPCOMR @ 0x00000004 snvs_rtc 30370000.snvs:snvs-rtc-lp: failed to enable rtc -110 snvs_rtc: probe of 30370000.snvs:snvs-rtc-lp failed with error -110 hctosys: unable to open rtc device (rtc0) Note bit 1 of LPCR is not set in the second case and is set in the first case and that bit 31 of HPCOMR is set in the second case but not in the first. Setting NPSWA_EN in HPCOMR allows us to boot through enabling TrustZone and continue onto the kernel. The kernel then has the necessary permissions to set LPCR::SRTC_ENV (RTC enable in the LP command register) whereas in contrast - in the failing case the non-privileged kernel cannot do so. This patch adds a simple init_snvs() call which sets the permission-bit called from soc.c for the i.MX7. It may be possible, safe and desirable to perform this on other i.MX processors but for now this is only tested on i.MX7 as working. Signed-off-by: Bryan O'Donoghue --- arch/arm/include/asm/mach-imx/sys_proto.h | 1 + arch/arm/mach-imx/mx7/Makefile | 2 +- arch/arm/mach-imx/mx7/snvs.c | 22 ++++++++++++++++++++++ arch/arm/mach-imx/mx7/soc.c | 2 ++ 4 files changed, 26 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-imx/mx7/snvs.c diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index 96795e1..aa51c0d 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -107,6 +107,7 @@ void set_chipselect_size(int const); void init_aips(void); void init_src(void); +void init_snvs(void); void imx_wdog_disable_powerdown(void); int board_mmc_get_env_dev(int devno); diff --git a/arch/arm/mach-imx/mx7/Makefile b/arch/arm/mach-imx/mx7/Makefile index ce289c1..e6bef6a 100644 --- a/arch/arm/mach-imx/mx7/Makefile +++ b/arch/arm/mach-imx/mx7/Makefile @@ -5,7 +5,7 @@ # # -obj-y := soc.o clock.o clock_slice.o ddr.o +obj-y := soc.o clock.o clock_slice.o ddr.o snvs.o ifdef CONFIG_ARMV7_PSCI obj-y += psci-mx7.o psci.o diff --git a/arch/arm/mach-imx/mx7/snvs.c b/arch/arm/mach-imx/mx7/snvs.c new file mode 100644 index 0000000..7e649b8 --- /dev/null +++ b/arch/arm/mach-imx/mx7/snvs.c @@ -0,0 +1,22 @@ +/* + * Copyright 2018 Linaro + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#define SNVS_HPCOMR 0x04 +#define SNVS_HPCOMR_NPSWA_EN BIT(31) + +void init_snvs(void) +{ + u32 val; + + /* Ensure SNVS HPCOMR sets NPSWA_EN to allow unpriv access to SNVS LP */ + val = readl(SNVS_BASE_ADDR + SNVS_HPCOMR); + val |= SNVS_HPCOMR_NPSWA_EN; + writel(val, SNVS_BASE_ADDR + SNVS_HPCOMR); +} diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c index fb92a26..3ceeeff 100644 --- a/arch/arm/mach-imx/mx7/soc.c +++ b/arch/arm/mach-imx/mx7/soc.c @@ -180,6 +180,8 @@ int arch_cpu_init(void) isolate_resource(); #endif + init_snvs(); + return 0; }