From patchwork Tue Jan 30 15:01:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Jacques Hiblot X-Patchwork-Id: 126252 Delivered-To: patch@linaro.org Received: by 10.46.84.92 with SMTP id y28csp3450786ljd; Tue, 30 Jan 2018 07:15:40 -0800 (PST) X-Google-Smtp-Source: AH8x225ZIO7tPLO1ctDS+IiIGRolX3n8UzU6qKRqjd+oBatbKsiLsORHrpGrGhbhiOcW3muO1uE9 X-Received: by 10.80.145.79 with SMTP id f15mr52877770eda.283.1517325340871; Tue, 30 Jan 2018 07:15:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517325340; cv=none; d=google.com; s=arc-20160816; b=zdy7xlUW47LdB2ebkLbs+cQhYDJvWrO+xz3dXtJcUi0NkX7kCtOThoQI7SW5e3RuEp SNUEW7zreuISLIdGC5FteKFhn88zXQ88Ju4lNoB7tIpDyE0VE6eL0gLwSe7stk6wQfht xfM0HCQoMJwmHQxQMVKV9+woy9iP4CPPi2t4J3Z52H+Pf5gTzMpVHTnH2hFtk/52F22x VueGIcDXoq1GYLFphKKfnohYDnOe/CiNglHfvynd+PXgCCaWq8gzHD6vLvnlCIMoxdkp KKDH2PoKks0aEc5wYRWRSO0xj4iUeb8JclMSHg/DGDnqCQH49pztCib5YaQY/w3rBQ7a Y++w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :cc:mime-version:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=6TQtSdh+ehnBsSig9kO1gpnOXCBOAjiPicYkp4/S7KA=; b=dOKv7o5KtttEKTpvfMHMoWPzXKsUIN3f1r5SZL53M2WVcfyofz9AB/TZIMlba7UQ9T BxTCohhqnY/yrFFIEMVjNPvjlsX5H1ukoniE7NIC3YdkXDr4YHmBg1/vSfIeW49xIabc RB/kxAOUymLtafqHxY/25XRhHTcUODkiRLg8TaeHgf7j29PBcJLA2TcWmts4XPKurw8X NnJw5hKUgcWElKDwl9Xc1ywok0CDnbBMSyWk/75G97PtkOIJh4OOfQKxLYd+kFqArVck qKYl5LfYtiSnqQkY2yrQskSmAa8dUfgfKk7mCtrBT/kNEl60RXPYjSVwUA1sWV+ocJpT 8pDg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=jJ/kW/0E; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id w36si5666701edd.51.2018.01.30.07.15.40; Tue, 30 Jan 2018 07:15:40 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=jJ/kW/0E; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 7D028C21E37; Tue, 30 Jan 2018 15:10:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 3C099C21DE5; Tue, 30 Jan 2018 15:04:59 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 8C8FBC21EC2; Tue, 30 Jan 2018 15:02:34 +0000 (UTC) Received: from lelnx193.ext.ti.com (lelnx193.ext.ti.com [198.47.27.77]) by lists.denx.de (Postfix) with ESMTPS id C8828C21E40 for ; Tue, 30 Jan 2018 15:02:28 +0000 (UTC) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id w0UF2RYo005688; Tue, 30 Jan 2018 09:02:27 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1517324547; bh=H8eWX13Nkht1JgtWxDkIZyJEkl4CtebKSqxvTiKCNQI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=jJ/kW/0E59otuxrixOG3ZAeS/z0uH2zaOglSeEhxZCmjiael8R6L5uq33S1Z2lFs8 01pr4F8nOMxB5bGz0vb+deTFQnjKZvjfO5/A0z3tV7vGgN0ob0HmsPeFBfoaaLnVII tg2FyLGdPN5e8bgzJgVTeRoJSkCWDE29haERxguQ= Received: from DFLE107.ent.ti.com (dfle107.ent.ti.com [10.64.6.28]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w0UF2RN9001738; Tue, 30 Jan 2018 09:02:27 -0600 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Tue, 30 Jan 2018 09:02:26 -0600 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Tue, 30 Jan 2018 09:02:26 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w0UF2QbT032396; Tue, 30 Jan 2018 09:02:26 -0600 From: Jean-Jacques Hiblot To: , , , Date: Tue, 30 Jan 2018 16:01:52 +0100 Message-ID: <1517324513-13875-24-git-send-email-jjhiblot@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1517324513-13875-1-git-send-email-jjhiblot@ti.com> References: <1517324513-13875-1-git-send-email-jjhiblot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v3 23/24] ARM: DRA7x/AM57x: Add MMC/SD fixups for rev1.0 and rev 1.1 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Kishon Vijay Abraham I Since DRA7xx/AM57xx SR1.1 and SR1.0 has errata to limit the frequency of MMC1 to 96MHz and frequency of MMC2 to 48MHz for AM572x SR1.1, limit the frequency and disable higher speed modes for those revision. Also use the recommended IO delays (those tagged with "rev11") Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Jean-Jacques Hiblot --- Changes in v3: None board/ti/am57xx/board.c | 30 ++++++++++++++++++++++++++++++ board/ti/dra7xx/evm.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 59 insertions(+) diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c index 1128784..9c1e2ef 100644 --- a/board/ti/am57xx/board.c +++ b/board/ti/am57xx/board.c @@ -30,6 +30,7 @@ #include #include #include +#include #include "../common/board_detect.h" #include "mux_data.h" @@ -815,6 +816,35 @@ int board_mmc_init(bd_t *bis) omap_mmc_init(1, 0, 0, -1, -1); return 0; } + +static const struct mmc_platform_fixups am57x_es1_1_mmc1_fixups = { + .hw_rev = "rev11", + .unsupported_caps = MMC_CAP(MMC_HS_200) | + MMC_CAP(UHS_SDR104), + .max_freq = 96000000, +}; + +static const struct mmc_platform_fixups am57x_es1_1_mmc23_fixups = { + .hw_rev = "rev11", + .unsupported_caps = MMC_CAP(MMC_HS_200) | + MMC_CAP(UHS_SDR104) | + MMC_CAP(UHS_SDR50), + .max_freq = 48000000, +}; + +const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr) +{ + switch (omap_revision()) { + case DRA752_ES1_0: + case DRA752_ES1_1: + if (addr == OMAP_HSMMC1_BASE) + return &am57x_es1_1_mmc1_fixups; + else + return &am57x_es1_1_mmc23_fixups; + default: + return NULL; + } +} #endif #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT) diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 6ecf971..c62724e 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -866,6 +866,35 @@ void board_mmc_poweron_ldo(uint voltage) palmas_mmc1_poweron_ldo(LDO1_VOLTAGE, LDO1_CTRL, voltage); } } + +static const struct mmc_platform_fixups dra7x_es1_1_mmc1_fixups = { + .hw_rev = "rev11", + .unsupported_caps = MMC_CAP(MMC_HS_200) | + MMC_CAP(UHS_SDR104), + .max_freq = 96000000, +}; + +static const struct mmc_platform_fixups dra7x_es1_1_mmc23_fixups = { + .hw_rev = "rev11", + .unsupported_caps = MMC_CAP(MMC_HS_200) | + MMC_CAP(UHS_SDR104) | + MMC_CAP(UHS_SDR50), + .max_freq = 48000000, +}; + +const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr) +{ + switch (omap_revision()) { + case DRA752_ES1_0: + case DRA752_ES1_1: + if (addr == OMAP_HSMMC1_BASE) + return &dra7x_es1_1_mmc1_fixups; + else + return &dra7x_es1_1_mmc23_fixups; + default: + return NULL; + } +} #endif #ifdef CONFIG_USB_DWC3