From patchwork Tue Jan 30 15:01:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Jacques Hiblot X-Patchwork-Id: 126243 Delivered-To: patch@linaro.org Received: by 10.46.84.92 with SMTP id y28csp3446312ljd; Tue, 30 Jan 2018 07:10:32 -0800 (PST) X-Google-Smtp-Source: AH8x225d73wQWKH1nzd8eBIa+zJd8lhtrog6wvJ2LxzYmHBGQ5h91aOwPaV7u17d+fi3BghBJh0A X-Received: by 10.80.178.99 with SMTP id o90mr5143776edd.255.1517325032677; Tue, 30 Jan 2018 07:10:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517325032; cv=none; d=google.com; s=arc-20160816; b=rQ4VJbGDwYM9G8TFoFcEJ8SdCgaUW6k7xP97qktNuSTIJvvSl0fj5aN0kWxO9LLagj esEvzdWqRRWXMMdlm/8r3lp1RKmzCLMF9cos3yamEkW8BYlU4U8ZiLmnlxYTxaWJn8zY ypbdlr6j51nYgI5kFs8C5qZep8SIq3IGPjw7ssAF1lMR29prEV+UIObVG+VcGFb47ZnH DtyWpjmXsqwjlkjqQrVKht10k6NSq0wFNhrU2q0Y7o+ntSal68ktgh3zLPQDU3+xnNlC hgN9tqhhaUV8mEXNHlGZDLEhkQuBgyNT4oZ0wcxoY8ipyWcXu/YfGgZ4gJHkw3iR4WXg euGA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :cc:mime-version:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=4VaxPb1EUXiHu0aay2cqxqEIUKGXp79LL0v10lqIE7k=; b=hjADg//jjCLCoDpi05DY3O2ERgv/tJYDsJPusbL5Gnq1xefDrw/BhDw//JwN8Aczf5 GHOufYDK114L730NRD72YGXqkqXuwjBA0pwwEKAwWbTP3/a6/TjAWxtuui08LU9xa0G+ dRyrlQJ69X2uIC8+sujK+v5XAJuSrI4gBbi3ofH7ee59x+zmTqYj8QprcY3mkpi6emgT bEMGDJ45mjjxEv6NRQp7oW1Y5Se8w4mKreu41DzF5t5J4ZlnmtII6R8kC1F+yslvW5z/ YMt8cWuYvaW3pSUlakKnH54FO5YiEqUlOfq7nDJT8dn71amm4Eqez1KmmLSd+J03D94y uywA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=sliEm6V6; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id g23si8327135edf.169.2018.01.30.07.10.32; Tue, 30 Jan 2018 07:10:32 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=sliEm6V6; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 4FEE4C21EA8; Tue, 30 Jan 2018 15:05:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 03623C21E40; Tue, 30 Jan 2018 15:02:40 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id D561DC21DA6; Tue, 30 Jan 2018 15:02:17 +0000 (UTC) Received: from lelnx193.ext.ti.com (lelnx193.ext.ti.com [198.47.27.77]) by lists.denx.de (Postfix) with ESMTPS id 21C1EC21E3A for ; Tue, 30 Jan 2018 15:02:12 +0000 (UTC) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id w0UF2Aui005641; Tue, 30 Jan 2018 09:02:10 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1517324530; bh=f/sd6mfJCtTQILJKzE3ZuywbqZsTaZtWupbczxg2ea8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=sliEm6V6WVwm2MKds0CkXvZqgfsvsYwyLAw7bZUM243EJgiFUxOSuFMGihlwZBOU2 MQkL/7wCRBIuBkc5qSGgjL8g0IVi5kXb7vmY28+pUfpY9dG0h7s9CKOK/ccMa8yZgS z0+uL9Mpyv90UwvweNNj0fTJg/RnyYK45nYK6Q9Y= Received: from DFLE106.ent.ti.com (dfle106.ent.ti.com [10.64.6.27]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w0UF2AYS001420; Tue, 30 Jan 2018 09:02:10 -0600 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Tue, 30 Jan 2018 09:02:10 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Tue, 30 Jan 2018 09:02:10 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w0UF29Eu027915; Tue, 30 Jan 2018 09:02:09 -0600 From: Jean-Jacques Hiblot To: , , , Date: Tue, 30 Jan 2018 16:01:39 +0100 Message-ID: <1517324513-13875-11-git-send-email-jjhiblot@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1517324513-13875-1-git-send-email-jjhiblot@ti.com> References: <1517324513-13875-1-git-send-email-jjhiblot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v3 10/24] ARM: OMAP5/DRA7: Enable iodelay recalibration to be done from uboot X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Kishon Vijay Abraham I Add a new API to perform iodelay recalibration without isolate io to be used in uboot. The data manual of J6/J6 Eco recommends to set different IODELAY values depending on the mode in which the MMC/SD is enumerated in order to ensure IO timings are met. The MMC driver can use the new API to set the IO delay values depending on the MMC mode. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Jean-Jacques Hiblot --- Changes in v3: None arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h | 3 +++ arch/arm/mach-omap2/omap5/dra7xx_iodelay.c | 30 ++++++++++++++++++++++++ include/configs/am57xx_evm.h | 2 -- include/configs/dra7xx_evm.h | 2 -- 4 files changed, 33 insertions(+), 4 deletions(-) diff --git a/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h b/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h index c997004..a8780ee 100644 --- a/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h +++ b/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h @@ -83,6 +83,9 @@ void __recalibrate_iodelay(struct pad_conf_entry const *pad, int npads, struct iodelay_cfg_entry const *iodelay, int niodelays); +void late_recalibrate_iodelay(struct pad_conf_entry const *pad, int npads, + struct iodelay_cfg_entry const *iodelay, + int niodelays); int __recalibrate_iodelay_start(void); void __recalibrate_iodelay_end(int ret); diff --git a/arch/arm/mach-omap2/omap5/dra7xx_iodelay.c b/arch/arm/mach-omap2/omap5/dra7xx_iodelay.c index 8798730..a9a9f75 100644 --- a/arch/arm/mach-omap2/omap5/dra7xx_iodelay.c +++ b/arch/arm/mach-omap2/omap5/dra7xx_iodelay.c @@ -272,3 +272,33 @@ err: __recalibrate_iodelay_end(ret); } + +void late_recalibrate_iodelay(struct pad_conf_entry const *pad, int npads, + struct iodelay_cfg_entry const *iodelay, + int niodelays) +{ + int ret = 0; + + /* unlock IODELAY CONFIG registers */ + writel(CFG_IODELAY_UNLOCK_KEY, (*ctrl)->iodelay_config_base + + CFG_REG_8_OFFSET); + + ret = calibrate_iodelay((*ctrl)->iodelay_config_base); + if (ret) + goto err; + + ret = update_delay_mechanism((*ctrl)->iodelay_config_base); + + /* Configure Mux settings */ + do_set_mux32((*ctrl)->control_padconf_core_base, pad, npads); + + /* Configure Manual IO timing modes */ + ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays); + if (ret) + goto err; + +err: + /* lock IODELAY CONFIG registers */ + writel(CFG_IODELAY_LOCK_KEY, (*ctrl)->iodelay_config_base + + CFG_REG_8_OFFSET); +} diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h index 7546b3f..65465d1 100644 --- a/include/configs/am57xx_evm.h +++ b/include/configs/am57xx_evm.h @@ -15,9 +15,7 @@ #include #include -#ifdef CONFIG_SPL_BUILD #define CONFIG_IODELAY_RECALIBRATION -#endif #define CONFIG_NR_DRAM_BANKS 2 diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index ff90b6d..975e6fd 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -14,9 +14,7 @@ #include -#ifdef CONFIG_SPL_BUILD #define CONFIG_IODELAY_RECALIBRATION -#endif #define CONFIG_VERY_BIG_RAM #define CONFIG_NR_DRAM_BANKS 2