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[81.169.180.215]) by mx.google.com with ESMTP id 35si3484542edp.500.2018.01.04.23.39.17; Thu, 04 Jan 2018 23:39:17 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=dmPewsJY; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.denx.de (Postfix, from userid 105) id 21053C21DC5; Fri, 5 Jan 2018 07:38:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 24A2FC21E14; Fri, 5 Jan 2018 07:38:12 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 6E2F6C21DC1; Fri, 5 Jan 2018 07:38:01 +0000 (UTC) Received: from mail-pg0-f68.google.com (mail-pg0-f68.google.com [74.125.83.68]) by lists.denx.de (Postfix) with ESMTPS id 61F44C21DE5 for ; Fri, 5 Jan 2018 07:37:59 +0000 (UTC) Received: by mail-pg0-f68.google.com with SMTP id 77so1723278pgd.8 for ; Thu, 04 Jan 2018 23:37:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=zg3tNK9l6yMwj8b1QUhOzU3EmxLV2FbRwO86A1s/d60=; b=dmPewsJY0dOSdBfqyj8utLLRdxc4merfU4jwsycWrNB1noGIMob7TtRUtY+2Dl9/1j dZN2oGi/rI4UkiKo0Ye494YtaMpUqoEOHudSxnSEcW1RWJcS4eN65R3KyechsVBSu99c uElD0XRnAJ5dRaE1PYTQ4jgMH6JawTwNx2JhQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=zg3tNK9l6yMwj8b1QUhOzU3EmxLV2FbRwO86A1s/d60=; b=TfL64f++Up2F2S8p1PIaeTpZWwe3C19YEUqwWW5CLNdlwr9rVUBveHMN2kamKhzJxG kRfT+0x5VQtrz+oMIHI1Uqr/8Z28gM88/n1VIpTetjUd4SVqzeZXOL1AFb5HEhBYJFqH Az96Fmuvsh+4RHzcvVh+/tki7iZ8SHfAtm6TtgWLE/3JcTZtnx/CPT2UBIsAkbUGsJAj pbLRlF8IsPilFNh1JTdnigZDE8UlKB15TlUVFAzy//J/X3Jqz1QABG4OZoX828/IrPu4 Ffww0joxONyx3pkjKpleVgeyRgWGPvRPt9L3eplyJSLKcjmktY2Fumlfpa+F9m4TLCqd tXYw== X-Gm-Message-State: AKGB3mKt/MkWI2VD7yOEl2U8crsqzHxdJ3ofJm2J8lLk3tIVeLORKfyn +OEhZlHjoOe8lUCXPuzxhPt0Zw== X-Received: by 10.101.82.205 with SMTP id z13mr1856532pgp.134.1515137878126; Thu, 04 Jan 2018 23:37:58 -0800 (PST) Received: from localhost.localdomain ([45.56.153.113]) by smtp.gmail.com with ESMTPSA id b9sm9553789pgs.3.2018.01.04.23.37.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 04 Jan 2018 23:37:57 -0800 (PST) From: Jun Nie To: wens@csie.org, maxime.ripard@free-electrons.com, hdegoede@redhat.com Date: Fri, 5 Jan 2018 15:37:00 +0800 Message-Id: <1515137821-30583-6-git-send-email-jun.nie@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1515137821-30583-1-git-send-email-jun.nie@linaro.org> References: <1515137821-30583-1-git-send-email-jun.nie@linaro.org> Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH 5/6] sunxi: usb_phy: Clear PHYCTL register before writing X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" PHYCTL register offset at 0x10 need to be cleared before it's written. Ported from below Linux patch. d699c1d phy: sun4i-usb: change PHYCTL register clearing code Signed-off-by: Jun Nie --- arch/arm/mach-sunxi/usb_phy.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-sunxi/usb_phy.c b/arch/arm/mach-sunxi/usb_phy.c index 2f1cad1..1a6b4b4 100644 --- a/arch/arm/mach-sunxi/usb_phy.c +++ b/arch/arm/mach-sunxi/usb_phy.c @@ -156,8 +156,14 @@ __maybe_unused static void usb_phy_write(struct sunxi_usb_phy *phy, int addr, static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy) { #if defined CONFIG_MACH_SUNXI_H3_H5 - if (phy->id == 0) + if (phy->id == 0) { +#if defined(CONFIG_USB_MUSB_HOST) clrbits_le32(SUNXI_USBPHY_BASE + REG_PHY_UNK_H3, 0x01); +#else + setbits_le32(SUNXI_USBPHY_BASE + REG_PHY_UNK_H3, 0x01); + writel(0, SUNXI_USB0_BASE + SUNXI_USB_CSR); +#endif + } #endif clrbits_le32(phy->base + REG_PMU_UNK_H3, 0x02); }