From patchwork Tue Nov 21 17:38:16 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 119386 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp5578875qgn; Tue, 21 Nov 2017 09:50:55 -0800 (PST) X-Google-Smtp-Source: AGs4zMbeJYRTTbqAwh/1z7dv2aNppc/sLkB+6neojCsMQto5KvUr9END36a15+1Hp1KZ3GCPvmh8 X-Received: by 10.80.131.38 with SMTP id 35mr25797743edh.291.1511286654918; Tue, 21 Nov 2017 09:50:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1511286654; cv=none; d=google.com; s=arc-20160816; b=hQzi+k2l88npgGNIId9esF8pNf/oawnUSQRG2uU2IqzJjvbUjQ73ehF+0LcPv8C0ZH owklrdVYhckEDd0UWlqkA8PwQ5Xx+lsbdhjGiT7r3G97sXZbIA9CDtFzMemkiCIBkYrm m577GFmgaH6T/I9VdAqpBn6O6QZYxTewObhN+1J+lR4ZGQGtRv0QQktOBpeBMvP2grpT eSfGwYSofQQ2nYlp+lDOpHUpqTmcgvXgWsBOOo+aeKsoEESIjn71egNlP1dE5eqGgw1C wuSMPjilzVAhW85KzJ1hHMYjVUp0c5ObmKzIQ+oY1KFKrDMM0K7I9uBH4TJOF7gdL80f eXug== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:dkim-signature:dkim-filter:arc-authentication-results; bh=enS+Op/g5bcvTYSwFJNSQYPJCxxzyaz8z91rdfW+wiM=; b=0OIJR5ZLMiX7yAjGiS+jME/8TaDeojHNlju6FI0JtPROi18RHXEH/CphSkdfSOzbxc uvNcfpnr8innZgKspoYqE6c7so2DFKS8HBnvzqxrzgw8KS84Pap4p22mqYl9gK8EUyig nQ+9G423exiI7LvQPW1RfxxQ/PHr9vWaeux9bitovrRO+IQorIxprMsDE8DAxEJQHQeE oBey4jLxai8HsQHfzaAMDqfzKuiGqtMdRlAq9WCqvzuWRoFaFi0OiiUaOjaLflDAik6E 9vu8PljVnrYz/1Y18saxulDLNk1KW3bDgMOz1GUIu7KtNZKZqhTeeX5Lvo7UqlCF3Fap n2CA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=fJbB28UR; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id 5si375526edl.353.2017.11.21.09.50.54; Tue, 21 Nov 2017 09:50:54 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=fJbB28UR; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id 4F908C21EE4; Tue, 21 Nov 2017 17:50:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 32632C21FED; Tue, 21 Nov 2017 17:39:40 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 0C2DCC21FC0; Tue, 21 Nov 2017 17:39:07 +0000 (UTC) Received: from conuserg-07.nifty.com (conuserg-07.nifty.com [210.131.2.74]) by lists.denx.de (Postfix) with ESMTPS id 270EDC21F4F for ; Tue, 21 Nov 2017 17:39:03 +0000 (UTC) Received: from grover.sesame (FL1-125-199-20-195.osk.mesh.ad.jp [125.199.20.195]) (authenticated) by conuserg-07.nifty.com with ESMTP id vALHcbtu001225; Wed, 22 Nov 2017 02:38:40 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-07.nifty.com vALHcbtu001225 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1511285920; bh=EzYJ46V/k8Zkifi7XwEWasaIbCKFk1T7L4+ighi1pnE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fJbB28UROYF3YoL843a3l1zQXdswY/ODRXXkoZSOBGAIZeJXulDR9dyTWgeFCJxv9 20iZIPlOwcOgat6XQTHi8an0Bx2wba/fcxS68ycqK//IV22P09NGoompzwb5mZPeeE q2a5si+tTUW4aNZ17qBWD2h3oID4FpGUjd4+aZGJs1dNqCdgh1hBMIrWJO4vBUAjqp RU/alONSfpUZmY4ZRDNjJZfn4azw7rb/K5B+BbLAvGd1Ty+A5lbocrb3z2WL1An8EU hlX4UmltXzJVSaAScBTCSfldZe4o4u8Xkra23226dNbxRllDakKHNtiol/lVS3eB8B h7IFC8IpupjdQ== X-Nifty-SrcIP: [125.199.20.195] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Wed, 22 Nov 2017 02:38:16 +0900 Message-Id: <1511285912-12452-7-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1511285912-12452-1-git-send-email-yamada.masahiro@socionext.com> References: <1511285912-12452-1-git-send-email-yamada.masahiro@socionext.com> Cc: Scott Wood Subject: [U-Boot] [PATCH 06/22] mtd: nand: Introduce nand_data_interface X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Sascha Hauer Currently we have no data structure to fully describe a NAND timing. We only have struct nand_sdr_timings for NAND timings in SDR mode, but nothing for DDR mode and also no container to store both types of timing. This patch adds struct nand_data_interface which stores the timing type and a union of different timings. This can be used to pass to drivers in order to configure the timing. Add kerneldoc for struct nand_sdr_timings while touching it anyway. Signed-off-by: Sascha Hauer Signed-off-by: Boris Brezillon [Linux commit: eee64b700e26b9bcc6fce024681c31f5e12271fc] Signed-off-by: Masahiro Yamada --- include/linux/mtd/nand.h | 166 +++++++++++++++++++++++++++++++++-------------- 1 file changed, 117 insertions(+), 49 deletions(-) diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index df00fd1..e321e3e 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -585,6 +585,123 @@ struct nand_buffers { }; /** + * struct nand_sdr_timings - SDR NAND chip timings + * + * This struct defines the timing requirements of a SDR NAND chip. + * These information can be found in every NAND datasheets and the timings + * meaning are described in the ONFI specifications: + * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing + * Parameters) + * + * All these timings are expressed in picoseconds. + * + * @tALH_min: ALE hold time + * @tADL_min: ALE to data loading time + * @tALS_min: ALE setup time + * @tAR_min: ALE to RE# delay + * @tCEA_max: CE# access time + * @tCEH_min: CE# high hold time + * @tCH_min: CE# hold time + * @tCHZ_max: CE# high to output hi-Z + * @tCLH_min: CLE hold time + * @tCLR_min: CLE to RE# delay + * @tCLS_min: CLE setup time + * @tCOH_min: CE# high to output hold + * @tCS_min: CE# setup time + * @tDH_min: Data hold time + * @tDS_min: Data setup time + * @tFEAT_max: Busy time for Set Features and Get Features + * @tIR_min: Output hi-Z to RE# low + * @tITC_max: Interface and Timing Mode Change time + * @tRC_min: RE# cycle time + * @tREA_max: RE# access time + * @tREH_min: RE# high hold time + * @tRHOH_min: RE# high to output hold + * @tRHW_min: RE# high to WE# low + * @tRHZ_max: RE# high to output hi-Z + * @tRLOH_min: RE# low to output hold + * @tRP_min: RE# pulse width + * @tRR_min: Ready to RE# low (data only) + * @tRST_max: Device reset time, measured from the falling edge of R/B# to the + * rising edge of R/B#. + * @tWB_max: WE# high to SR[6] low + * @tWC_min: WE# cycle time + * @tWH_min: WE# high hold time + * @tWHR_min: WE# high to RE# low + * @tWP_min: WE# pulse width + * @tWW_min: WP# transition to WE# low + */ +struct nand_sdr_timings { + u32 tALH_min; + u32 tADL_min; + u32 tALS_min; + u32 tAR_min; + u32 tCEA_max; + u32 tCEH_min; + u32 tCH_min; + u32 tCHZ_max; + u32 tCLH_min; + u32 tCLR_min; + u32 tCLS_min; + u32 tCOH_min; + u32 tCS_min; + u32 tDH_min; + u32 tDS_min; + u32 tFEAT_max; + u32 tIR_min; + u32 tITC_max; + u32 tRC_min; + u32 tREA_max; + u32 tREH_min; + u32 tRHOH_min; + u32 tRHW_min; + u32 tRHZ_max; + u32 tRLOH_min; + u32 tRP_min; + u32 tRR_min; + u64 tRST_max; + u32 tWB_max; + u32 tWC_min; + u32 tWH_min; + u32 tWHR_min; + u32 tWP_min; + u32 tWW_min; +}; + +/** + * enum nand_data_interface_type - NAND interface timing type + * @NAND_SDR_IFACE: Single Data Rate interface + */ +enum nand_data_interface_type { + NAND_SDR_IFACE, +}; + +/** + * struct nand_data_interface - NAND interface timing + * @type: type of the timing + * @timings: The timing, type according to @type + */ +struct nand_data_interface { + enum nand_data_interface_type type; + union { + struct nand_sdr_timings sdr; + } timings; +}; + +/** + * nand_get_sdr_timings - get SDR timing from data interface + * @conf: The data interface + */ +static inline const struct nand_sdr_timings * +nand_get_sdr_timings(const struct nand_data_interface *conf) +{ + if (conf->type != NAND_SDR_IFACE) + return ERR_PTR(-EINVAL); + + return &conf->timings.sdr; +} + +/** * struct nand_chip - NAND Private Flash Chip Data * @mtd: MTD device registered to the MTD framework * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the @@ -1059,55 +1176,6 @@ void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len); void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len); uint8_t nand_read_byte(struct mtd_info *mtd); -/* - * struct nand_sdr_timings - SDR NAND chip timings - * - * This struct defines the timing requirements of a SDR NAND chip. - * These informations can be found in every NAND datasheets and the timings - * meaning are described in the ONFI specifications: - * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing - * Parameters) - * - * All these timings are expressed in picoseconds. - */ - -struct nand_sdr_timings { - u32 tALH_min; - u32 tADL_min; - u32 tALS_min; - u32 tAR_min; - u32 tCEA_max; - u32 tCEH_min; - u32 tCH_min; - u32 tCHZ_max; - u32 tCLH_min; - u32 tCLR_min; - u32 tCLS_min; - u32 tCOH_min; - u32 tCS_min; - u32 tDH_min; - u32 tDS_min; - u32 tFEAT_max; - u32 tIR_min; - u32 tITC_max; - u32 tRC_min; - u32 tREA_max; - u32 tREH_min; - u32 tRHOH_min; - u32 tRHW_min; - u32 tRHZ_max; - u32 tRLOH_min; - u32 tRP_min; - u32 tRR_min; - u64 tRST_max; - u32 tWB_max; - u32 tWC_min; - u32 tWH_min; - u32 tWHR_min; - u32 tWP_min; - u32 tWW_min; -}; - /* get timing characteristics from ONFI timing mode. */ const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode);