From patchwork Tue Nov 21 17:38:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 119394 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp5583947qgn; Tue, 21 Nov 2017 09:55:22 -0800 (PST) X-Google-Smtp-Source: AGs4zMbdXME/AE0mQSiXnBFyTiYabk/M6TKS8ahvjrUca+E2cP+WKLSNfeevLZak5LrHPkkKilHo X-Received: by 10.80.140.176 with SMTP id q45mr22166352edq.186.1511286922258; Tue, 21 Nov 2017 09:55:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1511286922; cv=none; d=google.com; s=arc-20160816; b=0uFnRLTxIF+BurN+frZdIm4fF+KcqnAFc/S/6rJuthCJ+bgJHLx0PFIb/OODlMCwRP vyNeSA+VHNicvpI0zBUyqTd+E8EIrQmiB4Dbv8iwqZ1v5pi8z4BrPHfOaq1n+OMImsbx 1KvUKKwBfIwUqZPqq62OnZCzTW4DsKlTGFAlMNiSCBHY4H1bNCofcK4CF2Ezs4VHvSXH 3OPI7d5s4F6qoewVOGaBUwl7N2SoTh02ehbRzb7i7T2sXNgTyhm4EdvDhxVjhYr8RCx9 JArHISYBwZUav1i82ZOs5lEh7ZLaHl0pvdgJ6Z4oTm8MLrK9SN54VwOEGIjTHPu5DWLk OG7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:dkim-signature:dkim-filter:arc-authentication-results; bh=+MrRLXVoz7l4EL95sWHfGbKIT8a/nj69ueEbvptGWWA=; b=ilso+uWcV0y2x+kxQuztHMMaC7N8HcrZvK0YRlZA3GleIXXOnmz5dWDiFDqQcZ0M2g wGyIjOf8f6MxVMGb2dDzMMlHEsAZ2DO0JjBiaEHWhkQwy4vMs3jioF1DPX5uRJsI/knO v+thktMDGC8gaP9pYCDBQ8BZzOI3tIpy1YawZyqEeDo6HAyDk9fm5X7l0OioVrUY4PAH WLsEq4Tf6dG+xZbImps8fyuapyKVgbYPMso/8a9XgnNHXTtBeUVtu9Jxu9DpqKQjnsqf DH1ZRHo/R+b3dnJltmYVwmYtCgC0vZqPKW7q09XF50aJjRBjCNXDrftV4JWJ9GeLYjli MFhw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=xllqtWH0; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id i1si471286edl.225.2017.11.21.09.55.22; Tue, 21 Nov 2017 09:55:22 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=xllqtWH0; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id DD6FCC21FA9; Tue, 21 Nov 2017 17:52:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 4FC45C21FA9; Tue, 21 Nov 2017 17:39:53 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 654B8C22026; Tue, 21 Nov 2017 17:39:07 +0000 (UTC) Received: from conuserg-07.nifty.com (conuserg-07.nifty.com [210.131.2.74]) by lists.denx.de (Postfix) with ESMTPS id 59EE2C21F63 for ; Tue, 21 Nov 2017 17:39:04 +0000 (UTC) Received: from grover.sesame (FL1-125-199-20-195.osk.mesh.ad.jp [125.199.20.195]) (authenticated) by conuserg-07.nifty.com with ESMTP id vALHcbtr001225; Wed, 22 Nov 2017 02:38:39 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-07.nifty.com vALHcbtr001225 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1511285919; bh=bbroGEnVbfeY6ugEp7FF+RO+7ZFWtmWZNOxadp3p9WE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=xllqtWH0PW7InNLPvkno41ydOBBqbtFUO64jaNfBCd5Nw/Gck9FTs/qOwqp/zJYId 9iNP1JNp+n9cLi12mDF6KvMw4TGEoOIfP1H+iKnqOwcdtelPFctEEqEsxl/sZ7BG0X HWxmTTEsZ2DBk96hNJXA2k9Bybhz3GTEuS3sH5epBzaKfxG9Wv/n+RxoCMk9uiKH95 JRJIhdcx9o9PUKtXUScBMy26vOnaCn+YeTKFZs45lG+vAe7jnNHdjUnUnolRWddEXr eTMfkkzgnAoR+8hUjecf/bLfX8HznaN9K8LM/kzVZTiKGixb6YEDkSK2Ubdh7VwVMt CPDH2V47KNZlg== X-Nifty-SrcIP: [125.199.20.195] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Wed, 22 Nov 2017 02:38:13 +0900 Message-Id: <1511285912-12452-4-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1511285912-12452-1-git-send-email-yamada.masahiro@socionext.com> References: <1511285912-12452-1-git-send-email-yamada.masahiro@socionext.com> Cc: Scott Wood Subject: [U-Boot] [PATCH 03/22] mtd: nand: Add an option to maximize the ECC strength X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Boris Brezillon The generic NAND DT bindings allows one to tweak the ECC strength and step size to their need. It can be used to lower the ECC strength to match a bootloader/firmware config, but might also be used to get a better reliability. In the latter case, the user might want to use the maximum ECC strength without having to explicitly calculate the exact value (this value not only depends on the OOB size, but also on the NAND controller, and can be tricky to extract). Add a generic 'nand-ecc-maximize' DT property and the associated NAND_ECC_MAXIMIZE flag, to let ECC controller drivers select the best ECC strength and step-size on their own. Signed-off-by: Boris Brezillon Acked-by: Rob Herring [Linux commit: ba78ee00e1ff84de9b3ad33edbd3ec599099ee82] [masahiro: of_property_read_bool -> fdt_getprop for U-Boot] Signed-off-by: Masahiro Yamada --- drivers/mtd/nand/nand_base.c | 3 +++ include/linux/mtd/nand.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index efe3e4f..18f4169 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -3817,6 +3817,9 @@ static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, int node) if (ecc_step > 0) chip->ecc.size = ecc_step; + if (fdt_getprop(blob, node, "nand-ecc-maximize", NULL)) + chip->ecc.options |= NAND_ECC_MAXIMIZE; + return 0; } #else diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index cba6563..eebfb13 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -153,6 +153,7 @@ typedef enum { * pages and you want to rely on the default implementation. */ #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0) +#define NAND_ECC_MAXIMIZE BIT(1) /* Bit mask for flags passed to do_nand_read_ecc */ #define NAND_GET_DEVICE 0x80