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[81.169.180.215]) by mx.google.com with ESMTP id 61si38617edc.488.2017.10.13.03.32.46; Fri, 13 Oct 2017 03:32:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=etOHJuof; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id 706F8C21F1F; Fri, 13 Oct 2017 10:29:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 1A992C22027; Fri, 13 Oct 2017 10:22:57 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id A583CC21F16; Fri, 13 Oct 2017 10:22:41 +0000 (UTC) Received: from conuserg-12.nifty.com (conuserg-12.nifty.com [210.131.2.79]) by lists.denx.de (Postfix) with ESMTPS id BD785C21F32 for ; Fri, 13 Oct 2017 10:22:39 +0000 (UTC) Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-12.nifty.com with ESMTP id v9DAMGxL009903; Fri, 13 Oct 2017 19:22:26 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-12.nifty.com v9DAMGxL009903 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1507890146; bh=xq79XZuHtnjqF1pOCbUgq3XrnRpp4orXvntb6pkhBR4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=etOHJuofLu1ivZXh3zrj3Kjp5WkA1ZzJZtT1ngFSixfgYtMjQo/zLOQTPxjdhSrFy mhCTyvER3qWqc4Cqt8FHf6AKRqC4uUH95TB63wHaZAXj8aiv1g0N5s1Ab7PHNbIetK fFxkFoKwAXUdjzQcGDhDbJpwuW0lWBQdn57MBu3wk/Se9+DFiUBk2BZBB7yDn+mQyS bnivsZp0bCpIcX+czKeGhbrrTK3sy6VntW+0UVxZiAGYB0w3dVkPTwSW6km1C1/aBq qQWBZDJrtK1m7/duQQqGiizuYwpWd6mdzU8AR7LMMjl97nYw1WFedHFCbTAbP6S9HI 58U3n5iCq4u5g== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Fri, 13 Oct 2017 19:22:07 +0900 Message-Id: <1507890129-1543-19-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1507890129-1543-1-git-send-email-yamada.masahiro@socionext.com> References: <1507890129-1543-1-git-send-email-yamada.masahiro@socionext.com> Subject: [U-Boot] [PATCH 18/20] serial: uniphier: use clk for enable and get_rate X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Get clock rate from the clock driver to drop U-Boot specific property "clock-frequency". Signed-off-by: Masahiro Yamada --- drivers/serial/serial_uniphier.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/serial/serial_uniphier.c b/drivers/serial/serial_uniphier.c index 68895bd..a9d8b5c 100644 --- a/drivers/serial/serial_uniphier.c +++ b/drivers/serial/serial_uniphier.c @@ -6,7 +6,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include +#include #include #include #include @@ -90,11 +90,12 @@ static int uniphier_serial_pending(struct udevice *dev, bool input) static int uniphier_serial_probe(struct udevice *dev) { - DECLARE_GLOBAL_DATA_PTR; struct uniphier_serial_private_data *priv = dev_get_priv(dev); struct uniphier_serial __iomem *port; + struct clk clk; fdt_addr_t base; u32 tmp; + int ret; base = devfdt_get_addr(dev); if (base == FDT_ADDR_T_NONE) @@ -106,8 +107,15 @@ static int uniphier_serial_probe(struct udevice *dev) priv->membase = port; - priv->uartclk = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "clock-frequency", 0); + ret = clk_get_by_index(dev, 0, &clk); + if (ret) + return ret; + + ret = clk_enable(&clk); + if (ret) + return ret; + + priv->uartclk = clk_get_rate(&clk); tmp = readl(&port->lcr_mcr); tmp &= ~LCR_MASK;