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[81.169.180.215]) by mx.google.com with ESMTP id d89si715580edc.222.2017.10.13.03.22.48; Fri, 13 Oct 2017 03:22:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=WZZpCRj8; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id BAFE3C21D82; Fri, 13 Oct 2017 10:22:43 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 68FB2C21EEE; Fri, 13 Oct 2017 10:22:41 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 818BFC21F3D; Fri, 13 Oct 2017 10:22:40 +0000 (UTC) Received: from conuserg-12.nifty.com (conuserg-12.nifty.com [210.131.2.79]) by lists.denx.de (Postfix) with ESMTPS id 97908C21EEE for ; Fri, 13 Oct 2017 10:22:39 +0000 (UTC) Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-12.nifty.com with ESMTP id v9DAMGxH009903; Fri, 13 Oct 2017 19:22:23 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-12.nifty.com v9DAMGxH009903 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1507890144; bh=U/XLGL10xebfuiEwqZDu98pik34xFW50GrPEb1Nzf4A=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WZZpCRj8VP2TDpPvAskDMflEJ7nj+nkbcUYQyJBj0JhBAfl7zdXDmEnaL8nnCra5F 11rEP/QXdTmNlFqaCbG5MqNTIGQF3HEzjYei4P3kdbyO2LXqMKo+oZrR5stF4DH3+s ggBZUP6aLV6KEjDVcHAI+zbRUOzLuNAEqz8cpTk+3By5sbse04QDgpuKcuUaAFuqu1 BBpP8Re6CAACuMmb+ezEEQkL+FgG4ikDv+PoovJtHK2yycXq0uLul+6EOE9WiGYQJL C3tuD8Ze1jcl+XxPh2u5Z1Fd90iyh2s95ZuFBTtf0SZYD9lBffCJq3ANprVsSbikID WIAIdLCl4oKDg== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Fri, 13 Oct 2017 19:22:03 +0900 Message-Id: <1507890129-1543-15-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1507890129-1543-1-git-send-email-yamada.masahiro@socionext.com> References: <1507890129-1543-1-git-send-email-yamada.masahiro@socionext.com> Subject: [U-Boot] [PATCH 14/20] i2c: uniphier: use clk for enable and get_rate X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Get clock rate from the clock driver instead of hard-coding it. Signed-off-by: Masahiro Yamada Reviewed-by: Heiko Schocher --- drivers/i2c/i2c-uniphier.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/drivers/i2c/i2c-uniphier.c b/drivers/i2c/i2c-uniphier.c index 0f2734e..9100129 100644 --- a/drivers/i2c/i2c-uniphier.c +++ b/drivers/i2c/i2c-uniphier.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -36,8 +37,6 @@ struct uniphier_i2c_regs { u32 setup; /* setup time control */ }; -#define IOBUS_FREQ 100000000 - struct uniphier_i2c_priv { struct udevice *dev; struct uniphier_i2c_regs __iomem *regs; /* register base */ @@ -49,6 +48,8 @@ static int uniphier_i2c_probe(struct udevice *dev) { fdt_addr_t addr; struct uniphier_i2c_priv *priv = dev_get_priv(dev); + struct clk clk; + int ret; addr = devfdt_get_addr(dev); if (addr == FDT_ADDR_T_NONE) @@ -58,7 +59,19 @@ static int uniphier_i2c_probe(struct udevice *dev) if (!priv->regs) return -ENOMEM; - priv->input_clk = IOBUS_FREQ; + ret = clk_get_by_index(dev, 0, &clk); + if (ret < 0) { + dev_err(dev, "failed to get clock\n"); + return ret; + } + + ret = clk_enable(&clk); + if (ret) { + dev_err(dev, "failed to enable clock\n"); + return ret; + } + + priv->input_clk = clk_get_rate(&clk); priv->dev = dev;