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[81.169.180.215]) by mx.google.com with ESMTP id 24si229976edz.256.2017.10.12.20.49.20; Thu, 12 Oct 2017 20:49:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=HJJRih2r; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 51345C21F9D; Fri, 13 Oct 2017 03:49:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 3E5DDC21FB2; Fri, 13 Oct 2017 03:48:05 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 27950C21FAC; Fri, 13 Oct 2017 03:47:49 +0000 (UTC) Received: from lelnx194.ext.ti.com (lelnx194.ext.ti.com [198.47.27.80]) by lists.denx.de (Postfix) with ESMTPS id 62EDCC21F6C for ; Fri, 13 Oct 2017 03:47:45 +0000 (UTC) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id v9D3lhrm027019; Thu, 12 Oct 2017 22:47:43 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1507866463; bh=jsEe5HpSX0R0MQTT4ywe/JKZMPfW8JSNvmwxJToHr6Y=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=HJJRih2rjUR6unuAsy3le5p8xDkTLLQbQ8mjarU+NCNqyRQ7Xs8ttKRlW4JF1Xkv6 ujMxAI+MWj0rSz7gw6wbj3+6tbbB6mkH5r/6aByGW8aiPGKA+klTICwyJrJVrwPTz5 CKbpurmaV/rPSbJgOPIxDAKymmclSmwXYVmgbv3Q= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v9D3lh8H003377; Thu, 12 Oct 2017 22:47:43 -0500 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Thu, 12 Oct 2017 22:47:42 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Thu, 12 Oct 2017 22:47:43 -0500 Received: from droidlinux (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v9D3lhxd014654; Thu, 12 Oct 2017 22:47:43 -0500 Received: from praneeth by droidlinux with local (Exim 4.82) (envelope-from ) id 1e2qwo-0002pP-T7; Thu, 12 Oct 2017 22:47:42 -0500 From: Praneeth Bajjuri To: Praneeth Bajjuri , Date: Thu, 12 Oct 2017 22:47:04 -0500 Message-ID: <1507866425-10827-3-git-send-email-praneeth@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1507866425-10827-1-git-send-email-praneeth@ti.com> References: <1507866425-10827-1-git-send-email-praneeth@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: Tom Rini , Vishal Mahaveer Subject: [U-Boot] [PATCH 3/4] omap-common: fastboot: extend cpu type for DRA71x rev 2.1 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Vishal Mahaveer DRA71x processors are reduced pin and software compatible derivative of DRA72 processors. Extend support for this revision in "getvar cpu" command. Signed-off-by: Vishal Mahaveer [praneeth@ti.com: rebase to u-boot master] Signed-off-by: Praneeth Bajjuri Reviewed-by: Tom Rini --- arch/arm/mach-omap2/utils.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-omap2/utils.c b/arch/arm/mach-omap2/utils.c index d4f171b..2bd8290 100644 --- a/arch/arm/mach-omap2/utils.c +++ b/arch/arm/mach-omap2/utils.c @@ -33,6 +33,7 @@ static void omap_set_fastboot_cpu(void) break; case DRA722_ES1_0: case DRA722_ES2_0: + case DRA722_ES2_1: cpu = "DRA722"; break; default: