From patchwork Thu Sep 21 14:51:36 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Jacques Hiblot X-Patchwork-Id: 113272 Delivered-To: patch@linaro.org Received: by 10.80.163.150 with SMTP id s22csp1977210edb; Thu, 21 Sep 2017 07:54:34 -0700 (PDT) X-Google-Smtp-Source: AOwi7QBdgWSRfNKWFIWw0jhYn8U41TXiau02aX3VEuAPP46jQrYcV4zBIYcBfFaOGAmL5qO/pmzk X-Received: by 10.80.194.74 with SMTP id t10mr1472688edf.199.1506005674783; Thu, 21 Sep 2017 07:54:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506005674; cv=none; d=google.com; s=arc-20160816; b=ryQM7WHxvyTR4rO6MtJxY85Bqs+vKMSbt5QW4NQZoUf4RKgMjJdAdiRP0I2KNCE7Cd iXX20z3uvtck+YRIDW8E4Qv7K6kAys86O/xsq3HCagcfqYLPusxegBgn1sHHFW8tg4NK T79j04rMieNPkwt5SGXYDfsH7Raqb/H/Y99u+qsN3f9fK4Wi7j2U9UQp23BeRxKtXbjZ gTw3JHEom29Wbf2DbIEcXIWqgyYK3NGC2bA0L4sRRb25IvTiTu7KozijQ9wZRTnhp40u a9EjQgCCAMnPxoCXjZ/o4cgLRSV8ib4th3HBLi5Z0VYpyv80m1NETwQJHZezKB9juWYe dEjw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :cc:mime-version:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=g+4iQ1u4lR0N4zVb9tTgLQMUZYvyitYB/ZzK+sJ91HM=; b=YXrYqRUJYdWZrmiEwpBs8BQ8h/MUXHkJVmb0pW0VEZvUwFSxEce1ZlF4LMkYNNaRIB T4gOulmZo2LAUxLUlVohTc1PEoaiUyp+Buq5bBV3OcTMlF4YzgOYH8Aml6WUm1nmFgeD YI7MIBs1w5rHp8iugQioWW+m3bpyNxTTqce6gzSrGfRjdw23Id51Z3PiIOZug2ApBCrB J+T0YcDr00dANcI6ocdo4C+pGXk8P0QBWADGyFvLSUMn2btNceeCKG2YvSk9tuRyc9Mn E8H5q+wDz61r8lsJeD6dkjd4OXtDpljpNk3WzeeQfk4PHbZViCE9AJ+3oAt404WBgsE7 e2Nw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=P/Lgf0AE; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id 35si1530149edk.487.2017.09.21.07.54.34; Thu, 21 Sep 2017 07:54:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=P/Lgf0AE; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 5A999C2208E; Thu, 21 Sep 2017 14:53:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id A8FBAC21FE5; Thu, 21 Sep 2017 14:52:27 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C1D23C2202E; Thu, 21 Sep 2017 14:52:03 +0000 (UTC) Received: from lelnx193.ext.ti.com (lelnx193.ext.ti.com [198.47.27.77]) by lists.denx.de (Postfix) with ESMTPS id 31C23C21E48 for ; Thu, 21 Sep 2017 14:52:00 +0000 (UTC) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v8LEpwBD001778; Thu, 21 Sep 2017 09:51:58 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1506005518; bh=c8PJJGERbDCoJGEON2IYWWwRYrO6RKr48AOGE4O7s0Q=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=P/Lgf0AEeUBZR5/7yeiDNP2dLDolZtMghaPc7ywVlLN0mgTx+n8hegN7Uiq5AJrYo KK+sjPQMXAXrZwvXa//6F3MTA7G6qg3QG/1Ml+g+4lEtwmImauLPPTd/MGJzNhShSs KnjH+JD0WSZD3xwbLfsYlXK4mGMPfMYEVu4nfTRc= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LEpw2T019674; Thu, 21 Sep 2017 09:51:58 -0500 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Thu, 21 Sep 2017 09:51:57 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Thu, 21 Sep 2017 09:51:57 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LEpu6T022243; Thu, 21 Sep 2017 09:51:57 -0500 From: Jean-Jacques Hiblot To: , , , Date: Thu, 21 Sep 2017 16:51:36 +0200 Message-ID: <1506005496-8635-6-git-send-email-jjhiblot@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1506005496-8635-1-git-send-email-jjhiblot@ti.com> References: <1506005496-8635-1-git-send-email-jjhiblot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v2 5/5] mmc: omap_hsmmc: Fix incorrect bit operations for disabling a bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Kishon Vijay Abraham I omap_hsmmc driver uses "|" in a couple of places for disabling a bit. While it's okay to use it in "mmc_reg_out" (since mmc_reg_out has a _mask_ argument to take care of resetting a bit), it's incorrectly used for resetting flags in "omap_hsmmc_send_cmd". Fix it here by using "&= ~()" to reset a bit. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Jean-Jacques Hiblot Reviewed-by: Tom Rini --- arch/arm/include/asm/omap_mmc.h | 6 ++---- drivers/mmc/omap_hsmmc.c | 7 ++++--- 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h index 128cd81..bf9de9b 100644 --- a/arch/arm/include/asm/omap_mmc.h +++ b/arch/arm/include/asm/omap_mmc.h @@ -90,10 +90,9 @@ struct omap_hsmmc_plat { #define DMA_MASTER (0x1 << 20) #define BLEN_512BYTESLEN (0x200 << 0) #define NBLK_STPCNT (0x0 << 16) -#define DE_DISABLE (0x0 << 0) -#define BCE_DISABLE (0x0 << 1) +#define DE_ENABLE (0x1 << 0) #define BCE_ENABLE (0x1 << 1) -#define ACEN_DISABLE (0x0 << 2) +#define ACEN_ENABLE (0x1 << 2) #define DDIR_OFFSET (4) #define DDIR_MASK (0x1 << 4) #define DDIR_WRITE (0x0 << 4) @@ -134,7 +133,6 @@ struct omap_hsmmc_plat { #define ICS_NOTREADY (0x0 << 1) #define ICE_OSCILLATE (0x1 << 0) #define CEN_MASK (0x1 << 2) -#define CEN_DISABLE (0x0 << 2) #define CEN_ENABLE (0x1 << 2) #define CLKD_OFFSET (6) #define CLKD_MASK (0x3FF << 6) diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index fcda0e2..1c3d1a5 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -294,7 +294,7 @@ static int omap_hsmmc_init_setup(struct mmc *mmc) dsor = 240; mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), - (ICE_STOP | DTO_15THDTO | CEN_DISABLE)); + (ICE_STOP | DTO_15THDTO)); mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, (dsor << CLKD_OFFSET) | ICE_OSCILLATE); start = get_timer(0); @@ -542,7 +542,8 @@ static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, /* enable default flags */ flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK | - MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE); + MSBS_SGLEBLK); + flags &= ~(ACEN_ENABLE | BCE_ENABLE | DE_ENABLE); if (cmd->resp_type & MMC_RSP_CRC) flags |= CCCE_CHECK; @@ -809,7 +810,7 @@ static int omap_hsmmc_set_ios(struct udevice *dev) } mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), - (ICE_STOP | DTO_15THDTO | CEN_DISABLE)); + (ICE_STOP | DTO_15THDTO)); mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, (dsor << CLKD_OFFSET) | ICE_OSCILLATE);