From patchwork Fri Sep 15 12:43:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 112733 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp573979qgf; Fri, 15 Sep 2017 05:45:37 -0700 (PDT) X-Google-Smtp-Source: AOwi7QDRtYMBgAPTfgHfIcqQq4DpRp/tMUGghazQSR3qWRKh/DX0/2Dd8RJBXdiAnCypoBZOhZtD X-Received: by 10.80.146.194 with SMTP id l2mr5145369eda.71.1505479537744; Fri, 15 Sep 2017 05:45:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505479537; cv=none; d=google.com; s=arc-20160816; b=mUqjsfnPLVvDSGbCSc/CkWZSS4WE4cmeKZUxfd4QiuMjhxVKdp2cpasaAoVYURi/O7 ktEa3aYskkrjSd6bgQ6E7BjlP2KPZYnHCXgvYlMDNvlmwlNGtU3SswD+SBKOsIf85wiK L/76+9F6ZqbDrdTyqYP99Pqypd3BpL9RHdO25VJuSpt1r0RmslI/AJYDdTlv9/TwD4lL 2mIZ3swsv2FphUs72mnPfUtZGCKo5CzBfZm+4B9IqCNPPXAauP2cLC+ycwxLdrIdW/Te L5jUe7LsG1h+FjqSXQEC5ajz/tPEDxwYoQVVc4Q/ZxQ7RQgE1LLeA/kXmWmn06dsMF7H X0LQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:dkim-filter:arc-authentication-results; bh=mmwOLqZkFCZB3djKveJaOBNrp3RhUQEWTrLWA/4sp9M=; b=QWEG7e9G8tzhAQBLmzwwRVqer99ZIwx7UOLlOs1Tz6BRCeQktzRlkHIOBrrukm+dPJ hHgfBTFj0gzrPMW/vB71l9HpCLXLcCmcqrTEVFE0OtultuxcNHtJSV0094NQt8pPeGnx 3hwxSQK7EPC3YilgDZLXKFd/COOUlowF3pWLtSHADmPp/pyqgN3KxjimxIH6F9jtg+4s KslXl/kNjBykts/PO0CFd7vhAaPg09M6sNGBhrtZUJiozNE6YfynVhp8+9lGu3qA40vA FYhfinZMgRZZ0l01l5UVDBcncfnm6mJcQpnGr6cn/PNqQl42zk4lrUMDtEpevuXz5Xkr xE4g== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=gsct4I8C; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id u14si1018240edl.539.2017.09.15.05.45.37; Fri, 15 Sep 2017 05:45:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=gsct4I8C; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id 511E9C2201F; Fri, 15 Sep 2017 12:44:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 3601AC21FF5; Fri, 15 Sep 2017 12:44:56 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 34573C21F2A; Fri, 15 Sep 2017 12:44:17 +0000 (UTC) Received: from conuserg-11.nifty.com (conuserg-11.nifty.com [210.131.2.78]) by lists.denx.de (Postfix) with ESMTPS id C9332C21FF6 for ; Fri, 15 Sep 2017 12:44:16 +0000 (UTC) Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-11.nifty.com with ESMTP id v8FChYNx026429; Fri, 15 Sep 2017 21:43:54 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-11.nifty.com v8FChYNx026429 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1505479434; bh=7W8mAOOUVMszxzViYVtTIQqf9QEBAlrqlIOKf4OJE4w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=gsct4I8CfNts+mkzITf6m5AXuqoAd73npLTD90KL2osFzmgJjl10LKKElsHUWhW1p EvlUMqbDxdx9I7xQkYoIN20WxQQKtKanYjyXG3aRHckm5FhnK8lqL2mPrRRX2kG+sh n9O49Xnp63D5xxkn2rN56CLzYoec0rRKN9cBHspSIN/U2PGKbUfQgLgUOhpbMwzs/J i0S9mc/YBHOhIa/b5RWseA2+Ii7ZXfRQitmOXDrc4Vi7DuUztnrWYgPtTySYVn2Uhl 4mKKSN0l+ZJvLyo11BfeBOMDkAUCvEtZiojiCpxT4+IPW4j/DoGEDJmXm+eZyqDU55 4/pO5oFoLZCGg== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Fri, 15 Sep 2017 21:43:22 +0900 Message-Id: <1505479402-17945-4-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505479402-17945-1-git-send-email-yamada.masahiro@socionext.com> References: <1505479402-17945-1-git-send-email-yamada.masahiro@socionext.com> Subject: [U-Boot] [PATCH 4/4] ARM: uniphier: add GPU(Mali) reset deassert and clk enable X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The driver for Linux is out of control of Socionext, so set up reset / clock in here. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/clk/clk-ld20.c | 12 ++++++++++++ arch/arm/mach-uniphier/clk/clk-pxs3.c | 12 ++++++++++++ 2 files changed, 24 insertions(+) diff --git a/arch/arm/mach-uniphier/clk/clk-ld20.c b/arch/arm/mach-uniphier/clk/clk-ld20.c index 5bb560c..f79fb38 100644 --- a/arch/arm/mach-uniphier/clk/clk-ld20.c +++ b/arch/arm/mach-uniphier/clk/clk-ld20.c @@ -4,14 +4,26 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include #include #include "../init.h" +#include "../sc64-regs.h" #define SDCTRL_EMMC_HW_RESET 0x59810280 void uniphier_ld20_clk_init(void) { + u32 tmp; + + tmp = readl(SC_RSTCTRL6); + tmp |= BIT(8); /* Mali */ + writel(tmp, SC_RSTCTRL6); + + tmp = readl(SC_CLKCTRL6); + tmp |= BIT(8); /* Mali */ + writel(tmp, SC_CLKCTRL6); + /* TODO: use "mmc-pwrseq-emmc" */ writel(1, SDCTRL_EMMC_HW_RESET); } diff --git a/arch/arm/mach-uniphier/clk/clk-pxs3.c b/arch/arm/mach-uniphier/clk/clk-pxs3.c index 2dee857..3b9cc62 100644 --- a/arch/arm/mach-uniphier/clk/clk-pxs3.c +++ b/arch/arm/mach-uniphier/clk/clk-pxs3.c @@ -4,14 +4,26 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include #include #include "../init.h" +#include "../sc64-regs.h" #define SDCTRL_EMMC_HW_RESET 0x59810280 void uniphier_pxs3_clk_init(void) { + u32 tmp; + + tmp = readl(SC_RSTCTRL6); + tmp |= BIT(8); /* Mali */ + writel(tmp, SC_RSTCTRL6); + + tmp = readl(SC_CLKCTRL6); + tmp |= BIT(8); /* Mali */ + writel(tmp, SC_CLKCTRL6); + /* TODO: use "mmc-pwrseq-emmc" */ writel(1, SDCTRL_EMMC_HW_RESET); }