From patchwork Fri Sep 15 12:43:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 112732 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp573819qgf; Fri, 15 Sep 2017 05:45:26 -0700 (PDT) X-Google-Smtp-Source: AOwi7QDy3Nf7wwR3wBz0Pja1E7qS3Wkq8lQAK3ZVGF5fsVRIWZQzErt+kwWfo3wKhV4sWAq9Fkd2 X-Received: by 10.80.181.59 with SMTP id y56mr11365114edd.140.1505479526197; Fri, 15 Sep 2017 05:45:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505479526; cv=none; d=google.com; s=arc-20160816; b=i1Wfx2R4Oa6EhTHqODzgy+OMZPJM7s3dQSf8PS6YF2cP95hEeLPMzjK1sDbI1iO+zG lk2mOgJQtohreWzb4kLhHoSe+rXXn7/yzWPenuTfcj37CwSiUn54u0R7G/HmnCnHApOu jKLa/nOla5icbp16zHCAbkC7Epllf88VTZel3/TYjIrHHp8VmJ/ljBB9oeq1243jFeA7 pWg3hAf8LFJq5qVMoGv14mnI3n1/IkBOmDQHhtpkkgcSli/5YlGtcyEz4VQoN6+5nT22 Swd3/UxrXEmbJTkxLythWwqBu4rSGbSDX75O3kiJiEKzZjR82pOOCgS5O7dlMnouG6H0 aA4g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:dkim-signature:dkim-filter:arc-authentication-results; bh=de1Im0KkUca9VHx350O2rHBimV/NXciRC4mTEFNuCcA=; b=QTNGKKJq3HvMkDEq0nvHSkeSx7WoGOrctyoYWZGuY/8CToKfFKKmOMKP6ok4nXO2K5 XMJXZhFCZ+c9VC11G5EtyTR00dyK2LLt8eCcJ3hIdkNHLk8Ih4cmgEi5+nkdudHDE+oS e2jSHT7nNW6GmGQH7Be5ld4fnp3AuvV9M/rIVfV4gyWlWgez10X5zBlJpB99YYiiTRxN 2Z5mYff9mZp4SgrawvRHqOM5oOink0q/b5zl9GXm+5ZYC0IOBH8nRyE9zhQZEWr4YssN rxTMBSEj+ZhWPJz25MZk+yBCzmA+xPkpN3e7TEfW5sFRLSRGKKg60MsOCzSTQVeA26JJ ovGg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=RGYwcSUk; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id 63si1115997edy.413.2017.09.15.05.45.25; Fri, 15 Sep 2017 05:45:26 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=RGYwcSUk; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id CB24BC21FC6; Fri, 15 Sep 2017 12:44:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id EBD6AC2200D; Fri, 15 Sep 2017 12:44:34 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 373B1C21FBC; Fri, 15 Sep 2017 12:44:18 +0000 (UTC) Received: from conuserg-11.nifty.com (conuserg-11.nifty.com [210.131.2.78]) by lists.denx.de (Postfix) with ESMTPS id 205E6C22010 for ; Fri, 15 Sep 2017 12:44:16 +0000 (UTC) Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-11.nifty.com with ESMTP id v8FChYNw026429; Fri, 15 Sep 2017 21:43:50 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-11.nifty.com v8FChYNw026429 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1505479430; bh=5ndXK3JmBYE08oP9HeehPkMB4lAlvDDMGLbm8ddZoMo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RGYwcSUk0ZI7jwLZN+Puo144dEH/F9ZyYB4mMoWnGjMbuEb+ny1LQ5NMcBrZif6+V be3il/PMzSF8hLNl3YhslzRP5myrFbMdAqXHQ3OcDHLSF/xioDcXifxs/Q2iHMHuP3 OsQJ8yHhAIBzi1KeS9nCZ+X4oNsy9BbKHWw5Qr5fGrSkv+JABYnFaZUqzMw0axEaOp I4gQ7OOomOVT7LQF2TjVuiVoBd5ZafClaxkQBiy5SYgM1psJ/DGa+CYg+gyg9VCeOf SGZuW+guPR8YlN5OKGEDEUpyMwz9vyPwRsjVw66Qcxu7MVSARfTMQT6V5kTCmpyVPt ROblZrOnDd1qA== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Fri, 15 Sep 2017 21:43:21 +0900 Message-Id: <1505479402-17945-3-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505479402-17945-1-git-send-email-yamada.masahiro@socionext.com> References: <1505479402-17945-1-git-send-email-yamada.masahiro@socionext.com> Cc: Marek Vasut Subject: [U-Boot] [PATCH 3/4] ARM: uniphier: remove bit field macros from sc64-regs.h X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Starting from PXs3, the bit fields of RSTCTRL, CLKCTRL registers will change every SoC. There is no more point to define bitfields in the common header file. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/clk/clk-ld11.c | 2 +- arch/arm/mach-uniphier/sc64-regs.h | 18 ------------------ 2 files changed, 1 insertion(+), 19 deletions(-) diff --git a/arch/arm/mach-uniphier/clk/clk-ld11.c b/arch/arm/mach-uniphier/clk/clk-ld11.c index 0266e7e..a4b7419 100644 --- a/arch/arm/mach-uniphier/clk/clk-ld11.c +++ b/arch/arm/mach-uniphier/clk/clk-ld11.c @@ -40,7 +40,7 @@ void uniphier_ld11_clk_init(void) int ch; tmp = readl(SC_CLKCTRL4); - tmp |= SC_CLKCTRL4_MIO | SC_CLKCTRL4_STDMAC; + tmp |= BIT(10) | BIT(8); /* MIO, STDMAC */ writel(tmp, SC_CLKCTRL4); for (ch = 0; ch < 3; ch++) { diff --git a/arch/arm/mach-uniphier/sc64-regs.h b/arch/arm/mach-uniphier/sc64-regs.h index d0a51f2..80efb4e 100644 --- a/arch/arm/mach-uniphier/sc64-regs.h +++ b/arch/arm/mach-uniphier/sc64-regs.h @@ -15,34 +15,16 @@ #define SC_RSTCTRL (SC_BASE_ADDR | 0x2000) #define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008) #define SC_RSTCTRL4 (SC_BASE_ADDR | 0x200c) -#define SC_RSTCTRL4_ETHER (1 << 6) -#define SC_RSTCTRL4_NAND (1 << 0) #define SC_RSTCTRL5 (SC_BASE_ADDR | 0x2010) #define SC_RSTCTRL6 (SC_BASE_ADDR | 0x2014) #define SC_RSTCTRL7 (SC_BASE_ADDR | 0x2018) -#define SC_RSTCTRL7_UMCSB (1 << 16) -#define SC_RSTCTRL7_UMCA2 (1 << 10) -#define SC_RSTCTRL7_UMCA1 (1 << 9) -#define SC_RSTCTRL7_UMCA0 (1 << 8) -#define SC_RSTCTRL7_UMC32 (1 << 2) -#define SC_RSTCTRL7_UMC31 (1 << 1) -#define SC_RSTCTRL7_UMC30 (1 << 0) #define SC_CLKCTRL (SC_BASE_ADDR | 0x2100) #define SC_CLKCTRL3 (SC_BASE_ADDR | 0x2108) #define SC_CLKCTRL4 (SC_BASE_ADDR | 0x210c) -#define SC_CLKCTRL4_MIO (1 << 10) -#define SC_CLKCTRL4_STDMAC (1 << 8) -#define SC_CLKCTRL4_PERI (1 << 7) -#define SC_CLKCTRL4_ETHER (1 << 6) -#define SC_CLKCTRL4_NAND (1 << 0) #define SC_CLKCTRL5 (SC_BASE_ADDR | 0x2110) #define SC_CLKCTRL6 (SC_BASE_ADDR | 0x2114) #define SC_CLKCTRL7 (SC_BASE_ADDR | 0x2118) -#define SC_CLKCTRL7_UMCSB (1 << 16) -#define SC_CLKCTRL7_UMC32 (1 << 2) -#define SC_CLKCTRL7_UMC31 (1 << 1) -#define SC_CLKCTRL7_UMC30 (1 << 0) #define SC_CA72_GEARST (SC_BASE_ADDR | 0x8000) #define SC_CA72_GEARSET (SC_BASE_ADDR | 0x8004)