From patchwork Sat Aug 26 08:57:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 111047 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp2176633qge; Sat, 26 Aug 2017 02:00:40 -0700 (PDT) X-Received: by 10.80.172.166 with SMTP id x35mr1098331edc.209.1503738040156; Sat, 26 Aug 2017 02:00:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1503738040; cv=none; d=google.com; s=arc-20160816; b=QzcBNXh6PRsbD0UfSXkbrh8F9D6a7AOWAjZUSNkyG12AE3QHzIiGYZgg2d1Qum4mLA 5RmonrgssUcBWtkZyEZZNJO3rjocvywB8bysWXtA0U3vg2gNEX9Pt3f9zoXSiA1Rr/oq obZGezqmTl3add8awUcQpR48jWZKEGwFYE8EJ4dNjrhVPxcGJDi04W1ofDt5N+UoCwyj a+cZ0bbCqQxQUwgOx5/KPl7O/y4/mAkA8rdNLaeNFbrWNiEJXtIjDs/CKgWjRctkYLx7 qCMt8wdjsF1dLBQ4uqZSLdTJNblISIN1OsAikz5zt9AwUxc4wV3IWTmui23bVcFb2nbU GCJA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:dkim-signature:dkim-filter:arc-authentication-results; bh=1Y/iwob8ncIXyiGumMOAGVjR47jjuiJ0hZxJs0Gs5Lg=; b=IlQD+SPYxJB1fop3wK6tsHNMl7rF/7MdXFy85m6LcBUA443Ks21kufOAgM0aI0B98o HxQo8iohLQ6C3QcViaqO29u8UsdzNGpRDq/cJy2JO7+ih4g33VxA1HRRJK2JW1QCHwku O39xX0Qcw64NHkFwduywqu322aGJVSQUf9qQEDiaqtbUIJQxXm987W9Ho3unmIG0nan+ M5HVWJh5UH+8ckWnoCiAPbXj57+7V3J0Q/1vLrspmUSMxgIwj2F3S4eqBcPbSPlwx5zU j7d754iFMxFZlrZNDe+E7jgUuBJK5OOhKkOhPuG1VdfRDll65pebpNrgbVgaEVrBOKIR AMyg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=hGoiAghh; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id l5si1719028ede.402.2017.08.26.02.00.39; Sat, 26 Aug 2017 02:00:40 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=hGoiAghh; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id AEA30C22083; Sat, 26 Aug 2017 08:59:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 92836C2208B; Sat, 26 Aug 2017 08:58:39 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 66618C2206E; Sat, 26 Aug 2017 08:58:35 +0000 (UTC) Received: from conuserg-09.nifty.com (conuserg-09.nifty.com [210.131.2.76]) by lists.denx.de (Postfix) with ESMTPS id 126D1C2206E for ; Sat, 26 Aug 2017 08:58:33 +0000 (UTC) Received: from grover.sesame (FL1-122-131-185-176.osk.mesh.ad.jp [122.131.185.176]) (authenticated) by conuserg-09.nifty.com with ESMTP id v7Q8wANN031195; Sat, 26 Aug 2017 17:58:12 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com v7Q8wANN031195 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1503737892; bh=jVQtLSyRP5VoMUpJMBHGG+4wNWFvtYcPEMqT3mvFDs8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hGoiAghheBFVdY66JoJx0k95/E9k4RRl3/G8YYaQ/7vDRU/A06o+VHR1FGvW01zjk T5iumJFskz6cU7Ttr8i3WPHGC4n4JMIY2/x0kfSvHvbFZXueckBYXgJI8G0LXWAZVo co358xph8/6oOyF8HMid4TpjQQwknPb+CPZ/br6n/5b5GUCrj98NxeXQ9gAyY5a06X XKGUE53MVY7cffyPJQofYuWBCpPqTxux/2IhIaf+X0ihuKsb8BG+yp+HL1hEyU2z2o LBneBTpYvZw2ObLWs0uktn+O4nBhtAGFUElOjQrTpyh4XuUOtNKibf0sIA6v/o6RBr gzPQGaGD9kExQ== X-Nifty-SrcIP: [122.131.185.176] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Sat, 26 Aug 2017 17:57:59 +0900 Message-Id: <1503737883-14236-3-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503737883-14236-1-git-send-email-yamada.masahiro@socionext.com> References: <1503737883-14236-1-git-send-email-yamada.masahiro@socionext.com> Cc: Albert Aribaud Subject: [U-Boot] [PATCH 2/6] ARM: uniphier: move PLLCTRL register macros to each SoC .c file X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The new SoC PXs3 changed the address of PLL, but still uses the same PLL name. We can not define SC_*PLLCTRL in the common header. Move them to per-SoC .c file. Also, fix some PLL comments. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/clk/pll-ld11.c | 11 +++++++++++ arch/arm/mach-uniphier/clk/pll-ld20.c | 19 +++++++++++++++++++ arch/arm/mach-uniphier/sc64-regs.h | 21 --------------------- 3 files changed, 30 insertions(+), 21 deletions(-) diff --git a/arch/arm/mach-uniphier/clk/pll-ld11.c b/arch/arm/mach-uniphier/clk/pll-ld11.c index b4a97d21610f..1a7ec2952524 100644 --- a/arch/arm/mach-uniphier/clk/pll-ld11.c +++ b/arch/arm/mach-uniphier/clk/pll-ld11.c @@ -11,6 +11,17 @@ #include "../sc64-regs.h" #include "pll.h" +/* PLL type: SSC */ +#define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* CPU/ARM */ +#define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* misc */ +#define SC_MPLLCTRL (SC_BASE_ADDR | 0x1430) /* DSP */ +#define SC_VSPLLCTRL (SC_BASE_ADDR | 0x1440) /* Video codec, VPE etc. */ +#define SC_DPLLCTRL (SC_BASE_ADDR | 0x1460) /* DDR memory */ + +/* PLL type: VPLL27 */ +#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500) +#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520) + void uniphier_ld11_pll_init(void) { uniphier_ld20_sscpll_init(SC_CPLLCTRL, 1960, 1, 2); /* 2000MHz -> 1960MHz */ diff --git a/arch/arm/mach-uniphier/clk/pll-ld20.c b/arch/arm/mach-uniphier/clk/pll-ld20.c index 50b91598d64d..5e072c6dff77 100644 --- a/arch/arm/mach-uniphier/clk/pll-ld20.c +++ b/arch/arm/mach-uniphier/clk/pll-ld20.c @@ -11,6 +11,25 @@ #include "../sc64-regs.h" #include "pll.h" +/* PLL type: SSC */ +#define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* CPU/ARM */ +#define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* misc */ +#define SC_SPLL2CTRL (SC_BASE_ADDR | 0x1420) /* DSP */ +#define SC_MPLLCTRL (SC_BASE_ADDR | 0x1430) /* Video codec */ +#define SC_VPPLLCTRL (SC_BASE_ADDR | 0x1440) /* VPE etc. */ +#define SC_GPPLLCTRL (SC_BASE_ADDR | 0x1450) /* GPU/Mali */ +#define SC_DPLL0CTRL (SC_BASE_ADDR | 0x1460) /* DDR memory 0 */ +#define SC_DPLL1CTRL (SC_BASE_ADDR | 0x1470) /* DDR memory 1 */ +#define SC_DPLL2CTRL (SC_BASE_ADDR | 0x1480) /* DDR memory 2 */ + +/* PLL type: VPLL27 */ +#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500) +#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520) + +/* PLL type: DSPLL */ +#define SC_VPLL8KCTRL (SC_BASE_ADDR | 0x1540) +#define SC_A2PLLCTRL (SC_BASE_ADDR | 0x15C0) + void uniphier_ld20_pll_init(void) { uniphier_ld20_sscpll_init(SC_CPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4); diff --git a/arch/arm/mach-uniphier/sc64-regs.h b/arch/arm/mach-uniphier/sc64-regs.h index d3aa18530d97..d0a51f239c38 100644 --- a/arch/arm/mach-uniphier/sc64-regs.h +++ b/arch/arm/mach-uniphier/sc64-regs.h @@ -12,27 +12,6 @@ #define SC_BASE_ADDR 0x61840000 -/* PLL type: SSC */ -#define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* LD11/20: CPU/ARM */ -#define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* LD11/20: misc */ -#define SC_SPLL2CTRL (SC_BASE_ADDR | 0x1420) /* LD20: IPP */ -#define SC_MPLLCTRL (SC_BASE_ADDR | 0x1430) /* LD11/20: Video codec */ -#define SC_VSPLLCTRL (SC_BASE_ADDR | 0x1440) /* LD11 */ -#define SC_VPPLLCTRL (SC_BASE_ADDR | 0x1440) /* LD20: VPE etc. */ -#define SC_GPPLLCTRL (SC_BASE_ADDR | 0x1450) /* LD20: GPU/Mali */ -#define SC_DPLLCTRL (SC_BASE_ADDR | 0x1460) /* LD11: DDR memory */ -#define SC_DPLL0CTRL (SC_BASE_ADDR | 0x1460) /* LD20: DDR memory 0 */ -#define SC_DPLL1CTRL (SC_BASE_ADDR | 0x1470) /* LD20: DDR memory 1 */ -#define SC_DPLL2CTRL (SC_BASE_ADDR | 0x1480) /* LD20: DDR memory 2 */ - -/* PLL type: VPLL27 */ -#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500) -#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520) - -/* PLL type: DSPLL */ -#define SC_VPLL8KCTRL (SC_BASE_ADDR | 0x1540) -#define SC_A2PLLCTRL (SC_BASE_ADDR | 0x15C0) - #define SC_RSTCTRL (SC_BASE_ADDR | 0x2000) #define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008) #define SC_RSTCTRL4 (SC_BASE_ADDR | 0x200c)