diff mbox series

[5/5] mmc: omap_hsmmc: Fix incorrect bit operations for disabling a bit

Message ID 1499790014-29964-6-git-send-email-jjhiblot@ti.com
State New
Headers show
Series None | expand

Commit Message

Jean-Jacques Hiblot July 11, 2017, 4:20 p.m. UTC 
From: Kishon Vijay Abraham I <kishon@ti.com>

omap_hsmmc driver uses "|" in a couple of places for disabling a bit.
While it's okay to use it in "mmc_reg_out" (since mmc_reg_out has a
_mask_ argument to take care of resetting a bit), it's incorrectly used
for resetting flags in "omap_hsmmc_send_cmd".

Fix it here by using "&= ~()" to reset a bit.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
---
 arch/arm/include/asm/omap_mmc.h | 6 ++----
 drivers/mmc/omap_hsmmc.c        | 7 ++++---
 2 files changed, 6 insertions(+), 7 deletions(-)
diff mbox series

Patch

diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h
index 206badb..964bc5c 100644
--- a/arch/arm/include/asm/omap_mmc.h
+++ b/arch/arm/include/asm/omap_mmc.h
@@ -90,10 +90,9 @@  struct omap_hsmmc_plat {
 #define DMA_MASTER			(0x1 << 20)
 #define BLEN_512BYTESLEN		(0x200 << 0)
 #define NBLK_STPCNT			(0x0 << 16)
-#define DE_DISABLE			(0x0 << 0)
-#define BCE_DISABLE			(0x0 << 1)
+#define DE_ENABLE			(0x1 << 0)
 #define BCE_ENABLE			(0x1 << 1)
-#define ACEN_DISABLE			(0x0 << 2)
+#define ACEN_ENABLE			(0x1 << 2)
 #define DDIR_OFFSET			(4)
 #define DDIR_MASK			(0x1 << 4)
 #define DDIR_WRITE			(0x0 << 4)
@@ -134,7 +133,6 @@  struct omap_hsmmc_plat {
 #define ICS_NOTREADY			(0x0 << 1)
 #define ICE_OSCILLATE			(0x1 << 0)
 #define CEN_MASK			(0x1 << 2)
-#define CEN_DISABLE			(0x0 << 2)
 #define CEN_ENABLE			(0x1 << 2)
 #define CLKD_OFFSET			(6)
 #define CLKD_MASK			(0x3FF << 6)
diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index 3ee81bb..28865c0 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -287,7 +287,7 @@  static int omap_hsmmc_init_setup(struct mmc *mmc)
 
 	dsor = 240;
 	mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
-		(ICE_STOP | DTO_15THDTO | CEN_DISABLE));
+		(ICE_STOP | DTO_15THDTO));
 	mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
 		(dsor << CLKD_OFFSET) | ICE_OSCILLATE);
 	start = get_timer(0);
@@ -540,7 +540,8 @@  static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 
 	/* enable default flags */
 	flags =	flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
-			MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE);
+			MSBS_SGLEBLK);
+	flags &= ~(ACEN_ENABLE | BCE_ENABLE | DE_ENABLE);
 
 	if (cmd->resp_type & MMC_RSP_CRC)
 		flags |= CCCE_CHECK;
@@ -794,7 +795,7 @@  static int omap_hsmmc_set_ios(struct udevice *dev)
 	}
 
 	mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
-				(ICE_STOP | DTO_15THDTO | CEN_DISABLE));
+				(ICE_STOP | DTO_15THDTO));
 
 	mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
 				(dsor << CLKD_OFFSET) | ICE_OSCILLATE);