From patchwork Thu Jun 22 07:42:04 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 106176 Delivered-To: patch@linaro.org Received: by 10.140.91.2 with SMTP id y2csp2327658qgd; Thu, 22 Jun 2017 00:43:00 -0700 (PDT) X-Received: by 10.80.164.241 with SMTP id x46mr1568191edb.114.1498117379972; Thu, 22 Jun 2017 00:42:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1498117379; cv=none; d=google.com; s=arc-20160816; b=PCMqkIcL6/XTewfdJNB4zrkQyJHaXxBjtaOHLCqdSSnx0L1CTt3WU+M7UaX+8eK/TS 2BgDwlVXt0UPkoeAGAUfuJnWaVe1gq+Y4BfWonBHO42nUiOoEBPHnc9xxXmf9E+9pmZZ CJyTuW1Oim4aRcGG+Fudxqlc+m8Y/7No6n+2FH/3Nefx82Qtl9xOyUyaa94y41Ito0j7 gpQ8aAGNrr9uOgJ5lt5GQFopNGptbZHkR59Msm0Uef0oWzJI1gF1T0AdQeJFoBzljic6 jgaRMXDDKM0QkmbO3c0nVK594YdSy+08/5c0nIAXx1STtR8D9yTUKQjs8A+2hzBvDodO s6Ag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:message-id:date:to:from:dkim-signature :dkim-filter:arc-authentication-results; bh=70/jrlokmkybqZkioIwJ/yOft5Ow9+w/kfLGLtr4h9s=; b=xk/szAkKgfcCRbG0BCtJ+zm32g1F+GbVTqUga/+eOYvuX+TWzZVq7xKGHQxiRoUj2n rS+ZV2CA0SyhlKN2ac8tDA20z/SlgVF78ubV4R6IBXyUAwZm5dUL48tgB/gSiKDCzI42 XdDAE8jDPudVJDiFA8Y/9Q8ke2vZC6j4YrhKk/wQiYN7VmM2ypt6G8fF7glllmhUMpk6 XHxYLJKVbkLUDn+k3HV6rB1CVAboeAiUJJH+sCNR5jAIZ7cSEhWT2Po6bFV08+Un0+V3 tuvhF/tycsp+cUyhPpWs9mFqkiBvWCSxKl4aqe/Tuu+Rhr+7vd0B/KjAQXRE1yRuAP08 tKmw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.b=Wka/9JW7; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id z3si1242334edj.306.2017.06.22.00.42.59; Thu, 22 Jun 2017 00:42:59 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.b=Wka/9JW7; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id 7E21CC21C86; Thu, 22 Jun 2017 07:42:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 6EA16C21C4E; Thu, 22 Jun 2017 07:42:55 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 2A83BC21C4E; Thu, 22 Jun 2017 07:42:54 +0000 (UTC) Received: from conuserg-10.nifty.com (conuserg-10.nifty.com [210.131.2.77]) by lists.denx.de (Postfix) with ESMTPS id 04CF9C21C3E for ; Thu, 22 Jun 2017 07:42:52 +0000 (UTC) Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-10.nifty.com with ESMTP id v5M7gfVK001448; Thu, 22 Jun 2017 16:42:42 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-10.nifty.com v5M7gfVK001448 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1498117362; bh=GMjk12asXbH4l8b1kByOBgJ6BDoFHl0z9flFOT37mnU=; h=From:To:Cc:Subject:Date:From; b=Wka/9JW7xSrMZWVKrUcB/b+BfcXZk6E7+r+5/7gB9q9sU8lfB/oHCZDpJUCNeYt7X sErS8N/92vh6dhz2Zd4AY0Paz/qP7H5plk+ZZZKvZouqru+ARV5mkRG+d0AQ67uGZe iL1ZwoTAu0JHuVzAJYZAiOiYLcPAfbwskCaGBl99phb+1jx9U3G9rQRUVU9mI0YYYH mtFWweGLhI6PfgQi/6pf1jS9NNhhLsr5Y0CO+IpEfXxCTZB1zmHusyqJh7e+PVgQCD shHZw0m+KufsRuVW8+uPt+aXVfj/iFyeJ9rPbWmLOXH9mMX6sfJWqcNUlr43r8k/pv En/M3wqy8swgw== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Thu, 22 Jun 2017 16:42:04 +0900 Message-Id: <1498117324-15429-1-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 Subject: [U-Boot] [PATCH] ARM: uniphier: fix various sparse warnings X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Fix warnings reported by sparse: - ... was not declared. Should it be static?" - cast to restricted __be32 While fixing those, the type conflict of cci500_init() was found. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/arm64/arm-cci500.c | 2 ++ arch/arm/mach-uniphier/arm64/smp_kick_cpus.c | 2 ++ arch/arm/mach-uniphier/board_init.c | 2 +- arch/arm/mach-uniphier/clk/pll-pxs3.c | 2 ++ arch/arm/mach-uniphier/dram/umc-ld11.c | 14 +++++++------- arch/arm/mach-uniphier/dram/umc-pxs2.c | 2 +- arch/arm/mach-uniphier/dram_init.c | 1 + arch/arm/mach-uniphier/init.h | 3 ++- drivers/clk/uniphier/clk-uniphier-core.c | 2 +- drivers/reset/reset-uniphier.c | 18 +++++++++--------- 10 files changed, 28 insertions(+), 20 deletions(-) diff --git a/arch/arm/mach-uniphier/arm64/arm-cci500.c b/arch/arm/mach-uniphier/arm64/arm-cci500.c index f18595dc1311..bf0fad459bbd 100644 --- a/arch/arm/mach-uniphier/arm64/arm-cci500.c +++ b/arch/arm/mach-uniphier/arm64/arm-cci500.c @@ -11,6 +11,8 @@ #include #include +#include "../init.h" + #define CCI500_BASE 0x5FD00000 #define CCI500_SLAVE_OFFSET 0x1000 diff --git a/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c b/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c index 4f08963118a3..8e5b198c96ce 100644 --- a/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c +++ b/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c @@ -8,6 +8,8 @@ #include #include +#include "../init.h" + #define UNIPHIER_SMPCTRL_ROM_RSV0 0x59801200 void uniphier_smp_setup(void); diff --git a/arch/arm/mach-uniphier/board_init.c b/arch/arm/mach-uniphier/board_init.c index e05d6bffd5ce..ca910f6d7254 100644 --- a/arch/arm/mach-uniphier/board_init.c +++ b/arch/arm/mach-uniphier/board_init.c @@ -21,7 +21,7 @@ static void uniphier_setup_xirq(void) { const void *fdt = gd->fdt_blob; int soc_node, aidet_node; - const u32 *val; + const fdt32_t *val; unsigned long aidet_base; u32 tmp; diff --git a/arch/arm/mach-uniphier/clk/pll-pxs3.c b/arch/arm/mach-uniphier/clk/pll-pxs3.c index e29d9d000142..201d3517a86a 100644 --- a/arch/arm/mach-uniphier/clk/pll-pxs3.c +++ b/arch/arm/mach-uniphier/clk/pll-pxs3.c @@ -2,6 +2,8 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include "../init.h" + void uniphier_pxs3_pll_init(void) { } diff --git a/arch/arm/mach-uniphier/dram/umc-ld11.c b/arch/arm/mach-uniphier/dram/umc-ld11.c index 69aa4f2eebe3..9e2021a627e5 100644 --- a/arch/arm/mach-uniphier/dram/umc-ld11.c +++ b/arch/arm/mach-uniphier/dram/umc-ld11.c @@ -28,11 +28,11 @@ enum dram_size { }; /* PHY */ -const int rof_pos_shift_pre[RANK_BLOCKS_TR][2] = { {0, 0}, {0, 0} }; -const int rof_neg_shift_pre[RANK_BLOCKS_TR][2] = { {0, 0}, {0, 0} }; -const int rof_pos_shift[RANK_BLOCKS_TR][2] = { {-35, -35}, {-35, -35} }; -const int rof_neg_shift[RANK_BLOCKS_TR][2] = { {-17, -17}, {-17, -17} }; -const int tof_shift[RANK_BLOCKS_TR][2] = { {-50, -50}, {-50, -50} }; +static const int rof_pos_shift_pre[RANK_BLOCKS_TR][2] = { {0, 0}, {0, 0} }; +static const int rof_neg_shift_pre[RANK_BLOCKS_TR][2] = { {0, 0}, {0, 0} }; +static const int rof_pos_shift[RANK_BLOCKS_TR][2] = { {-35, -35}, {-35, -35} }; +static const int rof_neg_shift[RANK_BLOCKS_TR][2] = { {-17, -17}, {-17, -17} }; +static const int tof_shift[RANK_BLOCKS_TR][2] = { {-50, -50}, {-50, -50} }; /* Register address */ #define PHY_ZQ0CR1 0x00000184 @@ -65,7 +65,7 @@ const int tof_shift[RANK_BLOCKS_TR][2] = { {-50, -50}, {-50, -50} }; #define PHY_DSWBD_MASK 0x3F000000 /* bit[29:24] */ #define PHY_DSDQOE_MASK 0x00000FFF -static void ddrphy_maskwritel(u32 data, u32 mask, void *addr) +static void ddrphy_maskwritel(u32 data, u32 mask, void __iomem *addr) { u32 value; @@ -73,7 +73,7 @@ static void ddrphy_maskwritel(u32 data, u32 mask, void *addr) writel(value, addr); } -static u32 ddrphy_maskreadl(u32 mask, void *addr) +static u32 ddrphy_maskreadl(u32 mask, void __iomem *addr) { return readl(addr) & mask; } diff --git a/arch/arm/mach-uniphier/dram/umc-pxs2.c b/arch/arm/mach-uniphier/dram/umc-pxs2.c index 7fa29f119d08..8068ef13882e 100644 --- a/arch/arm/mach-uniphier/dram/umc-pxs2.c +++ b/arch/arm/mach-uniphier/dram/umc-pxs2.c @@ -436,7 +436,7 @@ static void umc_set_system_latency(void __iomem *dc_base, int phy_latency) } /* enable/disable auto refresh */ -void umc_refresh_ctrl(void __iomem *dc_base, int enable) +static void umc_refresh_ctrl(void __iomem *dc_base, int enable) { u32 tmp; diff --git a/arch/arm/mach-uniphier/dram_init.c b/arch/arm/mach-uniphier/dram_init.c index f79b7cf3ca67..6eb8d2650424 100644 --- a/arch/arm/mach-uniphier/dram_init.c +++ b/arch/arm/mach-uniphier/dram_init.c @@ -7,6 +7,7 @@ */ #include +#include #include #include #include diff --git a/arch/arm/mach-uniphier/init.h b/arch/arm/mach-uniphier/init.h index d413d00f951b..154918b18966 100644 --- a/arch/arm/mach-uniphier/init.h +++ b/arch/arm/mach-uniphier/init.h @@ -87,6 +87,7 @@ int uniphier_pro5_dpll_init(const struct uniphier_board_data *bd); int uniphier_pxs2_dpll_init(const struct uniphier_board_data *bd); int uniphier_ld11_dpll_init(const struct uniphier_board_data *bd); int uniphier_ld20_dpll_init(const struct uniphier_board_data *bd); +int uniphier_pxs3_dpll_init(const struct uniphier_board_data *bd); void uniphier_sld3_early_clk_init(void); void uniphier_ld11_early_clk_init(void); @@ -126,7 +127,7 @@ int uniphier_have_internal_stm(void); int uniphier_boot_from_backend(void); int uniphier_pin_init(const char *pinconfig_name); void uniphier_smp_kick_all_cpus(void); -void cci500_init(int nr_slaves); +void cci500_init(unsigned int nr_slaves); #undef pr_warn #define pr_warn(fmt, args...) printf(fmt, ##args) diff --git a/drivers/clk/uniphier/clk-uniphier-core.c b/drivers/clk/uniphier/clk-uniphier-core.c index d88bd62812d3..0fb48541b9b7 100644 --- a/drivers/clk/uniphier/clk-uniphier-core.c +++ b/drivers/clk/uniphier/clk-uniphier-core.c @@ -121,7 +121,7 @@ static ulong uniphier_clk_set_rate(struct clk *clk, ulong rate) return best_rate; } -const struct clk_ops uniphier_clk_ops = { +static const struct clk_ops uniphier_clk_ops = { .enable = uniphier_clk_enable, .get_rate = uniphier_clk_get_rate, .set_rate = uniphier_clk_set_rate, diff --git a/drivers/reset/reset-uniphier.c b/drivers/reset/reset-uniphier.c index e98df43bdb81..17e971a427f9 100644 --- a/drivers/reset/reset-uniphier.c +++ b/drivers/reset/reset-uniphier.c @@ -56,12 +56,12 @@ struct uniphier_reset_data { #define UNIPHIER_PRO4_SYS_RESET_USB3(id, ch) \ UNIPHIER_RESETX((id), 0x2000 + 0x4 * (ch), 17) -const struct uniphier_reset_data uniphier_sld3_sys_reset_data[] = { +static const struct uniphier_reset_data uniphier_sld3_sys_reset_data[] = { UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* Ether, HSC, MIO */ UNIPHIER_RESET_END, }; -const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = { +static const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = { UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* HSC, MIO, RLE */ UNIPHIER_PRO4_SYS_RESET_GIO(12), /* Ether, SATA, USB3 */ UNIPHIER_PRO4_SYS_RESET_USB3(14, 0), @@ -69,7 +69,7 @@ const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = { UNIPHIER_RESET_END, }; -const struct uniphier_reset_data uniphier_pro5_sys_reset_data[] = { +static const struct uniphier_reset_data uniphier_pro5_sys_reset_data[] = { UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* HSC */ UNIPHIER_PRO4_SYS_RESET_GIO(12), /* PCIe, USB3 */ UNIPHIER_PRO4_SYS_RESET_USB3(14, 0), @@ -77,7 +77,7 @@ const struct uniphier_reset_data uniphier_pro5_sys_reset_data[] = { UNIPHIER_RESET_END, }; -const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = { +static const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = { UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* HSC, RLE */ UNIPHIER_PRO4_SYS_RESET_USB3(14, 0), UNIPHIER_PRO4_SYS_RESET_USB3(15, 1), @@ -91,12 +91,12 @@ const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = { UNIPHIER_RESET_END, }; -const struct uniphier_reset_data uniphier_ld11_sys_reset_data[] = { +static const struct uniphier_reset_data uniphier_ld11_sys_reset_data[] = { UNIPHIER_LD11_SYS_RESET_STDMAC(8), /* HSC, MIO */ UNIPHIER_RESET_END, }; -const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = { +static const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = { UNIPHIER_LD11_SYS_RESET_STDMAC(8), /* HSC */ UNIPHIER_LD20_SYS_RESET_GIO(12), /* PCIe, USB3 */ UNIPHIER_RESETX(16, 0x200c, 12), /* USB30-PHY0 */ @@ -125,7 +125,7 @@ const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = { #define UNIPHIER_MIO_RESET_DMAC(id) \ UNIPHIER_RESETX((id), 0x110, 17) -const struct uniphier_reset_data uniphier_mio_reset_data[] = { +static const struct uniphier_reset_data uniphier_mio_reset_data[] = { UNIPHIER_MIO_RESET_SD(0, 0), UNIPHIER_MIO_RESET_SD(1, 1), UNIPHIER_MIO_RESET_SD(2, 2), @@ -155,7 +155,7 @@ const struct uniphier_reset_data uniphier_mio_reset_data[] = { #define UNIPHIER_PERI_RESET_FI2C(id, ch) \ UNIPHIER_RESETX((id), 0x114, 24 + (ch)) -const struct uniphier_reset_data uniphier_ld4_peri_reset_data[] = { +static const struct uniphier_reset_data uniphier_ld4_peri_reset_data[] = { UNIPHIER_PERI_RESET_UART(0, 0), UNIPHIER_PERI_RESET_UART(1, 1), UNIPHIER_PERI_RESET_UART(2, 2), @@ -168,7 +168,7 @@ const struct uniphier_reset_data uniphier_ld4_peri_reset_data[] = { UNIPHIER_RESET_END, }; -const struct uniphier_reset_data uniphier_pro4_peri_reset_data[] = { +static const struct uniphier_reset_data uniphier_pro4_peri_reset_data[] = { UNIPHIER_PERI_RESET_UART(0, 0), UNIPHIER_PERI_RESET_UART(1, 1), UNIPHIER_PERI_RESET_UART(2, 2),