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[81.169.180.215]) by mx.google.com with ESMTP id b7si7866189ede.94.2017.05.19.05.24.51; Fri, 19 May 2017 05:24:51 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id 892E5C221E6; Fri, 19 May 2017 12:24:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 04198C21D22; Fri, 19 May 2017 12:24:48 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 427B5C21D22; Fri, 19 May 2017 12:24:46 +0000 (UTC) Received: from conuserg-12.nifty.com (conuserg-12.nifty.com [210.131.2.79]) by lists.denx.de (Postfix) with ESMTPS id 0B946C21C84 for ; Fri, 19 May 2017 12:24:44 +0000 (UTC) Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-12.nifty.com with ESMTP id v4JCOPjw012185; Fri, 19 May 2017 21:24:26 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-12.nifty.com v4JCOPjw012185 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1495196666; bh=wRMf7s3i3+17aU9dN5n2gvVMtkdQtTI+Md7zdycgLBs=; h=From:To:Cc:Subject:Date:From; b=2I+I1qQRVsJ7SUBiMX49w3s4JDycdKb5gbL3ItLl3j3hbHvM2qpjpchgelKh+K+It mHmB4hnLJd7RVmjIVKMlb1HW+s0xlIKLL9TBotLE6K0JJ4Hvp1gqg40uBsReLz0nj3 yAb7pau92WjYD/M3uofkqfiRqT3IyCC3YsD9uYThl0bXwolAtHoVdj+AaP0EReXEr+ 4RMB0TYFtPieU6eDV6TsG4O6p6Qn57YA1FADk4jplsu8r8BRPNzkEXprvKtDBfCq2R x4Tbn9OkwkjiKAajdqazHFzmyhHrx8y/UEhPf+GnI/xG2rq7hYCSaJpwSTxRsMwUys ce49qMBtFXfGg== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Fri, 19 May 2017 21:24:23 +0900 Message-Id: <1495196663-18175-1-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 Subject: [U-Boot] [PATCH] mmc: sdhci-cadence: set timing mode register depending on frequency X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The MMC framework in U-Boot does not support a systematic API for timing switch like mmc_set_timing() in Linux. U-Boot just provides a hook to change the clock frequency via mmc_set_clock(). It is up to drivers if additional register settings are needed. This driver needs to set a correct timing mode into a register when it migrates to a different speed mode. Only increasing clock frequency could result in setup/hold timing violation. The timing mode should be decided by checking MMC_TIMING_* like drivers/mmc/host/sdhci-cadence.c in Linux, but "timing" is not supported by U-Boot for now. Just use mmc->clock to decide the timing mode. Signed-off-by: Masahiro Yamada --- drivers/mmc/sdhci-cadence.c | 48 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/drivers/mmc/sdhci-cadence.c b/drivers/mmc/sdhci-cadence.c index dc86d108a698..4e1c5f78a419 100644 --- a/drivers/mmc/sdhci-cadence.c +++ b/drivers/mmc/sdhci-cadence.c @@ -23,6 +23,18 @@ #define SDHCI_CDNS_HRS04_WDATA_SHIFT 8 #define SDHCI_CDNS_HRS04_ADDR_SHIFT 0 +#define SDHCI_CDNS_HRS06 0x18 /* eMMC control */ +#define SDHCI_CDNS_HRS06_TUNE_UP BIT(15) +#define SDHCI_CDNS_HRS06_TUNE_SHIFT 8 +#define SDHCI_CDNS_HRS06_TUNE_MASK 0x3f +#define SDHCI_CDNS_HRS06_MODE_MASK 0x7 +#define SDHCI_CDNS_HRS06_MODE_SD 0x0 +#define SDHCI_CDNS_HRS06_MODE_MMC_SDR 0x2 +#define SDHCI_CDNS_HRS06_MODE_MMC_DDR 0x3 +#define SDHCI_CDNS_HRS06_MODE_MMC_HS200 0x4 +#define SDHCI_CDNS_HRS06_MODE_MMC_HS400 0x5 +#define SDHCI_CDNS_HRS06_MODE_MMC_HS400ES 0x6 + /* SRS - Slot Register Set (SDHCI-compatible) */ #define SDHCI_CDNS_SRS_BASE 0x200 @@ -111,6 +123,41 @@ static int sdhci_cdns_phy_init(struct sdhci_cdns_plat *plat, return 0; } +static void sdhci_cdns_set_control_reg(struct sdhci_host *host) +{ + struct mmc *mmc = host->mmc; + struct sdhci_cdns_plat *plat = dev_get_platdata(mmc->dev); + unsigned int clock = mmc->clock; + u32 mode, tmp; + + /* + * REVISIT: + * The mode should be decided by MMC_TIMING_* like Linux, but + * U-Boot does not support timing. Use the clock frequency instead. + */ + if (clock <= 26000000) + mode = SDHCI_CDNS_HRS06_MODE_SD; /* use this for Legacy */ + else if (clock <= 52000000) { + if (mmc->ddr_mode) + mode = SDHCI_CDNS_HRS06_MODE_MMC_DDR; + else + mode = SDHCI_CDNS_HRS06_MODE_MMC_SDR; + } else { + /* The IP supports HS200/HS400, but U-Boot does not. */ + printf("unsupported frequency %d\n", clock); + return; + } + + tmp = readl(plat->hrs_addr + SDHCI_CDNS_HRS06); + tmp &= ~SDHCI_CDNS_HRS06_MODE_MASK; + tmp |= mode; + writel(tmp, plat->hrs_addr + SDHCI_CDNS_HRS06); +} + +static const struct sdhci_ops sdhci_cdns_ops = { + .set_control_reg = sdhci_cdns_set_control_reg, +}; + static int sdhci_cdns_bind(struct udevice *dev) { struct sdhci_cdns_plat *plat = dev_get_platdata(dev); @@ -137,6 +184,7 @@ static int sdhci_cdns_probe(struct udevice *dev) host->name = dev->name; host->ioaddr = plat->hrs_addr + SDHCI_CDNS_SRS_BASE; + host->ops = &sdhci_cdns_ops; host->quirks |= SDHCI_QUIRK_WAIT_SEND_CMD; ret = sdhci_cdns_phy_init(plat, gd->fdt_blob, dev->of_offset);