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[81.169.180.215]) by mx.google.com with ESMTP id r10si3765205edd.185.2017.05.12.06.49.27; Fri, 12 May 2017 06:49:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id 30AFBC21F08; Fri, 12 May 2017 13:49:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 476B0C21D09; Fri, 12 May 2017 13:49:22 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id DC266C21D09; Fri, 12 May 2017 13:49:20 +0000 (UTC) Received: from conuserg-10.nifty.com (conuserg-10.nifty.com [210.131.2.77]) by lists.denx.de (Postfix) with ESMTPS id D0498C21D01 for ; Fri, 12 May 2017 13:49:19 +0000 (UTC) Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-10.nifty.com with ESMTP id v4CDn48v013005; Fri, 12 May 2017 22:49:04 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-10.nifty.com v4CDn48v013005 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1494596944; bh=WDG5o7ENzdtA6rmYcgNRBtZwL+DCiRJhVLuQu0gJsmA=; h=From:To:Cc:Subject:Date:From; b=rPtjM/wo/ORLVMJhL9YFTW3naAacfnjAwzDF3XoRJVwf3m0KlP4g5g/KEzjEn/lpz gGDpXTy60mM+u7bp0ZnHlDnEv/s3IQwek8RZRR4WjomHyT2w6f59mKi4HNH8JEyfpq Cx+Nra8N09PhDZVTrV/1NugslDjAMNOgP03E3cQ++31zrMqD+U4Z4i7dRHPrXTsWDc 3Lvz86ZOdkDi0qwyaOux3OarIFYqvLwJcBTEzM06tmYmW2nuHpkC9P23f19Y7YKlCw dFqlITXxddgvTPeHdkam+CbI9FTm47UlA7+H/3qAybxeCinID2pwSwD9tBiOHvEKLr ULT5tHak6UlOA== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Fri, 12 May 2017 22:49:02 +0900 Message-Id: <1494596942-7976-1-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 Subject: [U-Boot] [PATCH v2] ARM: uniphier: add weird workaround code for LD20 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" When booting from ARM Trusted Firmware, U-Boot runs in EL1-NS. The boot flow is as follows: BL1 -> BL2 -> BL31 -> BL33 (i.e. U-Boot) This boot sequence works fine for LD11 SoC (Cortex-A53), but LD20 SoC (Cortex-A72) hangs in U-Boot. The solution I found is to read sctlr_el1 and write back the value as-is. This should be no effect, but surprisingly fixes the problem and LD20 SoC boots. I do not know why. Signed-off-by: Masahiro Yamada --- Changes in v2: - Compile it only for CONFIG_ARCH_UNIPHIER_LD20 arch/arm/mach-uniphier/arm64/Makefile | 2 ++ arch/arm/mach-uniphier/arm64/lowlevel_init.S | 17 +++++++++++++++++ 2 files changed, 19 insertions(+) create mode 100644 arch/arm/mach-uniphier/arm64/lowlevel_init.S diff --git a/arch/arm/mach-uniphier/arm64/Makefile b/arch/arm/mach-uniphier/arm64/Makefile index eb34c20..06072f2 100644 --- a/arch/arm/mach-uniphier/arm64/Makefile +++ b/arch/arm/mach-uniphier/arm64/Makefile @@ -9,5 +9,7 @@ obj-y += mem_map.o ifdef CONFIG_ARMV8_MULTIENTRY obj-y += smp.o smp_kick_cpus.o obj-$(CONFIG_ARCH_UNIPHIER_LD20) += arm-cci500.o +else +obj-$(CONFIG_ARCH_UNIPHIER_LD20) += lowlevel_init.o endif endif diff --git a/arch/arm/mach-uniphier/arm64/lowlevel_init.S b/arch/arm/mach-uniphier/arm64/lowlevel_init.S new file mode 100644 index 0000000..a4255bf --- /dev/null +++ b/arch/arm/mach-uniphier/arm64/lowlevel_init.S @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2017 Socionext Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +ENTRY(lowlevel_init) + /* + * I do not know why, but LD20 SoC (Cortex-A72) does not work + * without the following code. + */ + mrs x0, sctlr_el1 + msr sctlr_el1, x0 + ret +ENDPROC(lowlevel_init)