From patchwork Tue May 9 06:52:04 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 98871 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp1680745qge; Mon, 8 May 2017 23:52:43 -0700 (PDT) X-Received: by 10.80.143.5 with SMTP id 5mr18271384edy.68.1494312763277; Mon, 08 May 2017 23:52:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1494312763; cv=none; d=google.com; s=arc-20160816; b=jMbAzvvmn+21IURiQegQQ90XrCnbIm4yj5jbp2D152D5VBFGpJLyHJWEvhsxAJbY2C DYGfO8A4oJOE914nSyza/LAUmbfY0RjvzOCOJ3+WHKz3QdFafSHzyMDkvYuTc44CF1qZ pnzZT4fw2wqnVPFeQfU7ntegcL/fpqPhX3GTKoMkDXqLhfMA33PO54b+c2K4DM4oK4Jc r0yix8iAjq2+/SmP4d71RrHyTlCw4+41RLhKYLZP4RSoNQlhoNTdyf9xD6Mql+x6agC7 x8/f8Yyx2EmVl7jIMzEv1OE9FAzH9yKZ6zA9mQxwiSSn6VkiePiggSBc8gKGl/JWWZwS NYRg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:message-id:date:to:from:dkim-signature :dkim-filter:arc-authentication-results; bh=3PAztJOyoHnxvrVV9fPmx/ClIN8AdxStKMhbe5gpEmM=; b=0NHV04gr+szkuswj7F+nNzaeC2sPIIedfJJ7SLrnQqUuWij8SDMn0nfw0GbMivA6R8 /mNAtm/42rWpRGZaf9/O9rugs2pwo1fTaNXHNjx7nDsARJDRkABsT26wFge5quUjh/r2 +0IEDI3WWwRz0tQg1OZOI2JLqZ++Ny1bTUZUQvFvn6RBoifaDQguy3BnilVYQqz8IdXL G/ubMvmc0WumHzHMZ4reuI8VhyeF3I9kcaoOdJEs73YltxBj8oT9lASgrkV8O9SROJBM KnUoaHb3enB15CpSLJepBDzkPxI5I83bRqRxsWfBl5MfwJkI5O9zywLaMU4xXTj6ggF6 DSrw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id b7si12647665ede.94.2017.05.08.23.52.42; Mon, 08 May 2017 23:52:43 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id B892AC21C6B; Tue, 9 May 2017 06:52:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 42DBDC21C30; Tue, 9 May 2017 06:52:39 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 70F34C21C30; Tue, 9 May 2017 06:52:38 +0000 (UTC) Received: from conuserg-07.nifty.com (conuserg-07.nifty.com [210.131.2.74]) by lists.denx.de (Postfix) with ESMTPS id 77858C21C27 for ; Tue, 9 May 2017 06:52:37 +0000 (UTC) Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-07.nifty.com with ESMTP id v496q68S030755; Tue, 9 May 2017 15:52:06 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-07.nifty.com v496q68S030755 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1494312726; bh=H9Ad6gQfs6CHmDXFipYLQ6s3J8EfIEQjqHqRYBmLmgo=; h=From:To:Cc:Subject:Date:From; b=l7hcPWJGd9Tjvan8CZLpqukNQuILzemXLpKVHEJoi9vTKRCBdU4YICIE0b9Gd5Qoa iX6B0Et2YV4YcLaFohgmjmJr+exnKKnUbHnf3Zoz4kFI6ocELS/cY5Awot7mKPjFx+ m7lYP8lrLk8dlNlCa5qv/2KFAQIjk6ucS6fJojOYdxBr6WR/VPhxEMYHUytMkD/9i0 2SXY+phQUJSTrOfymi+A/v9yNzDQhdMcnFFMtIWpiCXG3kaxerKXvDm4XMg7aPcLGK k9XB+F/fvCbZ4CspNXPGzl7gdqVmKmYRv5MPybV6YbF3JshDH5mkIE8igQx/oXRcfP 3C2YnYBSKdqXw== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Tue, 9 May 2017 15:52:04 +0900 Message-Id: <1494312724-3091-1-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 Subject: [U-Boot] [PATCH v2] mmc: sdhci-cadence: import updates from Linux 4.12 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This driver is a counterpart of drivers/mmc/host/sdhci-cadence.c from Linux. Some updates for v4.12-rc1 can be imported to U-Boot. - Fix value of SDHCI_CDNS_HRS04_RDATA_SHIFT - Add polling for ACK bit to be sure that data are written to the PHY register - Retrieve PHY values from DT properties instead of fixed data The following is the list of upstream commits: - Linux commit 4e03f628b464e0580abadf5161eaa38c61d20943 mmc: sdhci-cadence: fix bit shift of read data from PHY port - Linux commit a0f8243229ed071c8da0ea7cedc1b7bf1b1515da mmc: sdhci-cadence: Fix writing PHY delay - Linux commit a89c472d8b55c5afc4c79e6e3d1338730034eb01 mmc: sdhci-cadence: Update PHY delay configuration Signed-off-by: Masahiro Yamada --- Changes in v2: - Add missing "commit" to git-log drivers/mmc/sdhci-cadence.c | 67 ++++++++++++++++++++++++++++++++++++++------- 1 file changed, 57 insertions(+), 10 deletions(-) diff --git a/drivers/mmc/sdhci-cadence.c b/drivers/mmc/sdhci-cadence.c index 2253bbc..dc86d10 100644 --- a/drivers/mmc/sdhci-cadence.c +++ b/drivers/mmc/sdhci-cadence.c @@ -7,8 +7,10 @@ #include #include +#include #include #include +#include #include #include @@ -17,7 +19,7 @@ #define SDHCI_CDNS_HRS04_ACK BIT(26) #define SDHCI_CDNS_HRS04_RD BIT(25) #define SDHCI_CDNS_HRS04_WR BIT(24) -#define SDHCI_CDNS_HRS04_RDATA_SHIFT 12 +#define SDHCI_CDNS_HRS04_RDATA_SHIFT 16 #define SDHCI_CDNS_HRS04_WDATA_SHIFT 8 #define SDHCI_CDNS_HRS04_ADDR_SHIFT 0 @@ -34,6 +36,9 @@ #define SDHCI_CDNS_PHY_DLY_EMMC_LEGACY 0x06 #define SDHCI_CDNS_PHY_DLY_EMMC_SDR 0x07 #define SDHCI_CDNS_PHY_DLY_EMMC_DDR 0x08 +#define SDHCI_CDNS_PHY_DLY_SDCLK 0x0b +#define SDHCI_CDNS_PHY_DLY_HSMMC 0x0c +#define SDHCI_CDNS_PHY_DLY_STROBE 0x0d struct sdhci_cdns_plat { struct mmc_config cfg; @@ -41,11 +46,31 @@ struct sdhci_cdns_plat { void __iomem *hrs_addr; }; -static void sdhci_cdns_write_phy_reg(struct sdhci_cdns_plat *plat, - u8 addr, u8 data) +struct sdhci_cdns_phy_cfg { + const char *property; + u8 addr; +}; + +static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] = { + { "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, }, + { "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, }, + { "cdns,phy-input-delay-sd-uhs-sdr12", SDHCI_CDNS_PHY_DLY_UHS_SDR12, }, + { "cdns,phy-input-delay-sd-uhs-sdr25", SDHCI_CDNS_PHY_DLY_UHS_SDR25, }, + { "cdns,phy-input-delay-sd-uhs-sdr50", SDHCI_CDNS_PHY_DLY_UHS_SDR50, }, + { "cdns,phy-input-delay-sd-uhs-ddr50", SDHCI_CDNS_PHY_DLY_UHS_DDR50, }, + { "cdns,phy-input-delay-mmc-highspeed", SDHCI_CDNS_PHY_DLY_EMMC_SDR, }, + { "cdns,phy-input-delay-mmc-ddr", SDHCI_CDNS_PHY_DLY_EMMC_DDR, }, + { "cdns,phy-dll-delay-sdclk", SDHCI_CDNS_PHY_DLY_SDCLK, }, + { "cdns,phy-dll-delay-sdclk-hsmmc", SDHCI_CDNS_PHY_DLY_HSMMC, }, + { "cdns,phy-dll-delay-strobe", SDHCI_CDNS_PHY_DLY_STROBE, }, +}; + +static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_plat *plat, + u8 addr, u8 data) { void __iomem *reg = plat->hrs_addr + SDHCI_CDNS_HRS04; u32 tmp; + int ret; tmp = (data << SDHCI_CDNS_HRS04_WDATA_SHIFT) | (addr << SDHCI_CDNS_HRS04_ADDR_SHIFT); @@ -54,17 +79,36 @@ static void sdhci_cdns_write_phy_reg(struct sdhci_cdns_plat *plat, tmp |= SDHCI_CDNS_HRS04_WR; writel(tmp, reg); + ret = readl_poll_timeout(reg, tmp, tmp & SDHCI_CDNS_HRS04_ACK, 10); + if (ret) + return ret; + tmp &= ~SDHCI_CDNS_HRS04_WR; writel(tmp, reg); + + return 0; } -static void sdhci_cdns_phy_init(struct sdhci_cdns_plat *plat) +static int sdhci_cdns_phy_init(struct sdhci_cdns_plat *plat, + const void *fdt, int nodeoffset) { - sdhci_cdns_write_phy_reg(plat, SDHCI_CDNS_PHY_DLY_SD_HS, 4); - sdhci_cdns_write_phy_reg(plat, SDHCI_CDNS_PHY_DLY_SD_DEFAULT, 4); - sdhci_cdns_write_phy_reg(plat, SDHCI_CDNS_PHY_DLY_EMMC_LEGACY, 9); - sdhci_cdns_write_phy_reg(plat, SDHCI_CDNS_PHY_DLY_EMMC_SDR, 2); - sdhci_cdns_write_phy_reg(plat, SDHCI_CDNS_PHY_DLY_EMMC_DDR, 3); + const u32 *prop; + int ret, i; + + for (i = 0; i < ARRAY_SIZE(sdhci_cdns_phy_cfgs); i++) { + prop = fdt_getprop(fdt, nodeoffset, + sdhci_cdns_phy_cfgs[i].property, NULL); + if (!prop) + continue; + + ret = sdhci_cdns_write_phy_reg(plat, + sdhci_cdns_phy_cfgs[i].addr, + fdt32_to_cpu(*prop)); + if (ret) + return ret; + } + + return 0; } static int sdhci_cdns_bind(struct udevice *dev) @@ -76,6 +120,7 @@ static int sdhci_cdns_bind(struct udevice *dev) static int sdhci_cdns_probe(struct udevice *dev) { + DECLARE_GLOBAL_DATA_PTR; struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); struct sdhci_cdns_plat *plat = dev_get_platdata(dev); struct sdhci_host *host = dev_get_priv(dev); @@ -94,7 +139,9 @@ static int sdhci_cdns_probe(struct udevice *dev) host->ioaddr = plat->hrs_addr + SDHCI_CDNS_SRS_BASE; host->quirks |= SDHCI_QUIRK_WAIT_SEND_CMD; - sdhci_cdns_phy_init(plat); + ret = sdhci_cdns_phy_init(plat, gd->fdt_blob, dev->of_offset); + if (ret) + return ret; ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0); if (ret)