From patchwork Tue May 9 04:40:54 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 98869 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp1644676qge; Mon, 8 May 2017 21:41:25 -0700 (PDT) X-Received: by 10.80.134.115 with SMTP id 48mr20167904edt.26.1494304885311; Mon, 08 May 2017 21:41:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1494304885; cv=none; d=google.com; s=arc-20160816; b=yS/XPSaOhfXQUdwiPSHlhiTtSM41/HzwGHfwEEDYMJ98229g2f+WOA+RUdB4S1c6J+ eSXJ13nqHl7SqW7QZLpM+DCb+eGCYg+K0l2K5IeiID3tKHIuKr8ACOvvfG4dmMDbtXIY NkNmsyJx0ggbfBap86T64ZMedRGjhLKP2lNlRdLwSxyaDf6wo43qtIhDfoCRUHPdpQU/ 8RM0Hb0+2Td+QeJvdcw/TPWffV7Pd6Gx+wUbBDD1iZbrYLp4oWcmyBmIja0psgaffQrZ YXXMmyKc7WI0PTz3rzBzf3KFfIFNhwAu1xTfQyg1i0KQ0qUyphzRplxvF2BJVGMlr4Eg MTEg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:message-id:date:to:from:dkim-signature :dkim-filter:arc-authentication-results; bh=oH+Yn0krP2zD5fxEc+zpB56SdRrgj9KqzjDYgajR2sg=; b=UQHO7TYoSzJ5tDtEoN8wGUECmXRXO5cl0paH4l6CoKVDh+I9MPikYdgOlEK2Q1KDlJ 02cshbXKDBZCDKh1AKk+yGsW1HBfgofouaFCbVnjCuY+JlA3GhGvfkUaYFgCrq5BxbpK nFRSNzUkoZbeZlhsTqZsZnA72JTb02ObSZaflxA7BYbukPTe1iXEC4tsOvMjOD7+f4JW L8BFa+OFjE6vVJFtIFgKsT7USO42cosVp1fEE4UQIoKbTMmIg1L2eSJKHM1OY3/wDTHI 5RaYWPjdQIpsb//o3rzDDwnL6VH6L89Baifl5Y7u0MTywtkk9Jwn9pQrMA7kMfpAiQZu 0V+Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id y38si11944325ede.270.2017.05.08.21.41.24; Mon, 08 May 2017 21:41:25 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id C0899C21C64; Tue, 9 May 2017 04:41:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 5FC5CC21C3A; Tue, 9 May 2017 04:41:21 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 72FBBC21C3A; Tue, 9 May 2017 04:41:20 +0000 (UTC) Received: from conuserg-10.nifty.com (conuserg-10.nifty.com [210.131.2.77]) by lists.denx.de (Postfix) with ESMTPS id 69555C21C27 for ; Tue, 9 May 2017 04:41:19 +0000 (UTC) Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-10.nifty.com with ESMTP id v494eujc005229; Tue, 9 May 2017 13:40:56 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-10.nifty.com v494eujc005229 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1494304857; bh=fxmOr6Vtx/HFiktKtZEi3EUtNOLz+yi21JzktoytHbM=; h=From:To:Cc:Subject:Date:From; b=MVSB2KNXlXv4Rzninnpv7YMj+Mgsjq5LDzhwR+iYwx+S6Ff6oJ6dMCciKzRqP84C2 zHbsHCJqWThEi37NC2VaqX/swt7QvyLX65OIo3pNJmHWmyRX/58BljSQ7DdbYZoLZi gw23zJYZxUsP933WvQyTH2LyLONnLFrdHwxnltOZcoFavgFtFKmsNQLY8wPBMNEi58 Fjq9Hsqsgod//FsgTI3AY7XO2524pgo1VtDyjVABFKG/QxPsT+wdEbVgABi2PBW67o kyuQIK9uncgQuk+/nJzS4uyXkEX8bx1bGG7FWl4hw/KeMARfuJSvBt7AnLIvaHBCG4 nNcwAP8fGxQgQ== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Tue, 9 May 2017 13:40:54 +0900 Message-Id: <1494304854-28341-1-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 Subject: [U-Boot] [PATCH] mmc: sdhci-cadence: import updates from Linux 4.12 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This driver is a counterpart of drivers/mmc/host/sdhci-cadence.c from Linux. Some updates for v4.12-rc1 can be imported to U-Boot. - Fix value of SDHCI_CDNS_HRS04_RDATA_SHIFT - Add polling for ACK bit to be sure that data are written to the PHY register - Retrieve PHY values from DT properties instead of fixed data The following is the list of upstream commits: - Linux commit 4e03f628b464e0580abadf5161eaa38c61d20943 mmc: sdhci-cadence: fix bit shift of read data from PHY port - Linux commit a0f8243229ed071c8da0ea7cedc1b7bf1b1515da mmc: sdhci-cadence: Fix writing PHY delay - Linux a89c472d8b55c5afc4c79e6e3d1338730034eb01 mmc: sdhci-cadence: Update PHY delay configuration Signed-off-by: Masahiro Yamada --- drivers/mmc/sdhci-cadence.c | 67 ++++++++++++++++++++++++++++++++++++++------- 1 file changed, 57 insertions(+), 10 deletions(-) diff --git a/drivers/mmc/sdhci-cadence.c b/drivers/mmc/sdhci-cadence.c index 2253bbc..dc86d10 100644 --- a/drivers/mmc/sdhci-cadence.c +++ b/drivers/mmc/sdhci-cadence.c @@ -7,8 +7,10 @@ #include #include +#include #include #include +#include #include #include @@ -17,7 +19,7 @@ #define SDHCI_CDNS_HRS04_ACK BIT(26) #define SDHCI_CDNS_HRS04_RD BIT(25) #define SDHCI_CDNS_HRS04_WR BIT(24) -#define SDHCI_CDNS_HRS04_RDATA_SHIFT 12 +#define SDHCI_CDNS_HRS04_RDATA_SHIFT 16 #define SDHCI_CDNS_HRS04_WDATA_SHIFT 8 #define SDHCI_CDNS_HRS04_ADDR_SHIFT 0 @@ -34,6 +36,9 @@ #define SDHCI_CDNS_PHY_DLY_EMMC_LEGACY 0x06 #define SDHCI_CDNS_PHY_DLY_EMMC_SDR 0x07 #define SDHCI_CDNS_PHY_DLY_EMMC_DDR 0x08 +#define SDHCI_CDNS_PHY_DLY_SDCLK 0x0b +#define SDHCI_CDNS_PHY_DLY_HSMMC 0x0c +#define SDHCI_CDNS_PHY_DLY_STROBE 0x0d struct sdhci_cdns_plat { struct mmc_config cfg; @@ -41,11 +46,31 @@ struct sdhci_cdns_plat { void __iomem *hrs_addr; }; -static void sdhci_cdns_write_phy_reg(struct sdhci_cdns_plat *plat, - u8 addr, u8 data) +struct sdhci_cdns_phy_cfg { + const char *property; + u8 addr; +}; + +static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] = { + { "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, }, + { "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, }, + { "cdns,phy-input-delay-sd-uhs-sdr12", SDHCI_CDNS_PHY_DLY_UHS_SDR12, }, + { "cdns,phy-input-delay-sd-uhs-sdr25", SDHCI_CDNS_PHY_DLY_UHS_SDR25, }, + { "cdns,phy-input-delay-sd-uhs-sdr50", SDHCI_CDNS_PHY_DLY_UHS_SDR50, }, + { "cdns,phy-input-delay-sd-uhs-ddr50", SDHCI_CDNS_PHY_DLY_UHS_DDR50, }, + { "cdns,phy-input-delay-mmc-highspeed", SDHCI_CDNS_PHY_DLY_EMMC_SDR, }, + { "cdns,phy-input-delay-mmc-ddr", SDHCI_CDNS_PHY_DLY_EMMC_DDR, }, + { "cdns,phy-dll-delay-sdclk", SDHCI_CDNS_PHY_DLY_SDCLK, }, + { "cdns,phy-dll-delay-sdclk-hsmmc", SDHCI_CDNS_PHY_DLY_HSMMC, }, + { "cdns,phy-dll-delay-strobe", SDHCI_CDNS_PHY_DLY_STROBE, }, +}; + +static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_plat *plat, + u8 addr, u8 data) { void __iomem *reg = plat->hrs_addr + SDHCI_CDNS_HRS04; u32 tmp; + int ret; tmp = (data << SDHCI_CDNS_HRS04_WDATA_SHIFT) | (addr << SDHCI_CDNS_HRS04_ADDR_SHIFT); @@ -54,17 +79,36 @@ static void sdhci_cdns_write_phy_reg(struct sdhci_cdns_plat *plat, tmp |= SDHCI_CDNS_HRS04_WR; writel(tmp, reg); + ret = readl_poll_timeout(reg, tmp, tmp & SDHCI_CDNS_HRS04_ACK, 10); + if (ret) + return ret; + tmp &= ~SDHCI_CDNS_HRS04_WR; writel(tmp, reg); + + return 0; } -static void sdhci_cdns_phy_init(struct sdhci_cdns_plat *plat) +static int sdhci_cdns_phy_init(struct sdhci_cdns_plat *plat, + const void *fdt, int nodeoffset) { - sdhci_cdns_write_phy_reg(plat, SDHCI_CDNS_PHY_DLY_SD_HS, 4); - sdhci_cdns_write_phy_reg(plat, SDHCI_CDNS_PHY_DLY_SD_DEFAULT, 4); - sdhci_cdns_write_phy_reg(plat, SDHCI_CDNS_PHY_DLY_EMMC_LEGACY, 9); - sdhci_cdns_write_phy_reg(plat, SDHCI_CDNS_PHY_DLY_EMMC_SDR, 2); - sdhci_cdns_write_phy_reg(plat, SDHCI_CDNS_PHY_DLY_EMMC_DDR, 3); + const u32 *prop; + int ret, i; + + for (i = 0; i < ARRAY_SIZE(sdhci_cdns_phy_cfgs); i++) { + prop = fdt_getprop(fdt, nodeoffset, + sdhci_cdns_phy_cfgs[i].property, NULL); + if (!prop) + continue; + + ret = sdhci_cdns_write_phy_reg(plat, + sdhci_cdns_phy_cfgs[i].addr, + fdt32_to_cpu(*prop)); + if (ret) + return ret; + } + + return 0; } static int sdhci_cdns_bind(struct udevice *dev) @@ -76,6 +120,7 @@ static int sdhci_cdns_bind(struct udevice *dev) static int sdhci_cdns_probe(struct udevice *dev) { + DECLARE_GLOBAL_DATA_PTR; struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); struct sdhci_cdns_plat *plat = dev_get_platdata(dev); struct sdhci_host *host = dev_get_priv(dev); @@ -94,7 +139,9 @@ static int sdhci_cdns_probe(struct udevice *dev) host->ioaddr = plat->hrs_addr + SDHCI_CDNS_SRS_BASE; host->quirks |= SDHCI_QUIRK_WAIT_SEND_CMD; - sdhci_cdns_phy_init(plat); + ret = sdhci_cdns_phy_init(plat, gd->fdt_blob, dev->of_offset); + if (ret) + return ret; ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0); if (ret)