From patchwork Sun Jan 15 05:59:08 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 91517 Delivered-To: patch@linaro.org Received: by 10.140.20.99 with SMTP id 90csp888618qgi; Sat, 14 Jan 2017 22:00:27 -0800 (PST) X-Received: by 10.223.136.206 with SMTP id g14mr17863293wrg.52.1484460027064; Sat, 14 Jan 2017 22:00:27 -0800 (PST) Return-Path: Received: from theia.denx.de (theia.denx.de. [85.214.87.163]) by mx.google.com with ESMTP id a19si7980352wmd.119.2017.01.14.22.00.26; Sat, 14 Jan 2017 22:00:27 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) client-ip=85.214.87.163; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C27E5B38E4; Sun, 15 Jan 2017 07:00:13 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id FvMm1Nwk1wjh; Sun, 15 Jan 2017 07:00:13 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 12B91A760B; Sun, 15 Jan 2017 07:00:01 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 41219A75C2 for ; Sun, 15 Jan 2017 06:59:40 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id nXYkQsAtFZ66 for ; Sun, 15 Jan 2017 06:59:40 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from conuserg-10.nifty.com (conuserg-10.nifty.com [210.131.2.77]) by theia.denx.de (Postfix) with ESMTPS id 272E8A75CC for ; Sun, 15 Jan 2017 06:59:36 +0100 (CET) Received: from grover.sesame (FL1-111-169-71-157.osk.mesh.ad.jp [111.169.71.157]) (authenticated) by conuserg-10.nifty.com with ESMTP id v0F5xD3l016694; Sun, 15 Jan 2017 14:59:20 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-10.nifty.com v0F5xD3l016694 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1484459960; bh=bd893VKJzyn3TIS/OHAw2tyhO93jx/Vp3SLFCRDZg28=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Y9OjdAKZOedmohG6qJ6p/2Fswx3Y+83raJkcxJWRECLxYDH2bNqRBsIYGW6190BmA qJukRE9DvdTSkjP8E09b9eGR1TumrA0FcYYmSmN/CbfCy4W5HSmwA1NVnVpGmeK+WV JASdcikvTqWwo+jVvBK9llIxFu8jqrCPUS2KzK/+svWfERXoALOHXrA8L+U41AJFIR qrH7P8aUiZk9n9G1tgK0rOw98SIJiS47e/KlVkGmGjkRbQoCBOj2+UnSn3MfZRkLRO GEDCO28n4HZdq/sVfcFNI5OiGzjbJgPOu3iowFvHj6besH/PPaCT00Ob2E2rexkjj/ RkOgpkKsJV5rQ== X-Nifty-SrcIP: [111.169.71.157] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Sun, 15 Jan 2017 14:59:08 +0900 Message-Id: <1484459950-8644-8-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1484459950-8644-1-git-send-email-yamada.masahiro@socionext.com> References: <1484459950-8644-1-git-send-email-yamada.masahiro@socionext.com> Cc: Albert Aribaud Subject: [U-Boot] [PATCH 7/9] ARM: uniphier: refactor board_init() X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The code here is cluttered due to the switch statement. Introduce a table of callbacks to clean up the initialization code across SoCs. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/board_init.c | 219 +++++++++++++++++++++++------------- 1 file changed, 140 insertions(+), 79 deletions(-) -- 2.7.4 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot diff --git a/arch/arm/mach-uniphier/board_init.c b/arch/arm/mach-uniphier/board_init.c index 4cab7fe..77f1fb0 100644 --- a/arch/arm/mach-uniphier/board_init.c +++ b/arch/arm/mach-uniphier/board_init.c @@ -48,116 +48,177 @@ static void uniphier_setup_xirq(void) writel(tmp, 0x55000090); } -static void uniphier_nand_pin_init(bool cs2) +#ifdef CONFIG_ARCH_UNIPHIER_LD11 +static void uniphier_ld11_misc_init(void) { -#ifdef CONFIG_NAND_DENALI - if (uniphier_pin_init(cs2 ? "nand2cs_grp" : "nand_grp")) - pr_err("failed to init NAND pins\n"); -#endif + sg_set_pinsel(149, 14, 8, 4); /* XIRQ0 -> XIRQ0 */ + sg_set_iectrl(149); + sg_set_pinsel(153, 14, 8, 4); /* XIRQ4 -> XIRQ4 */ + sg_set_iectrl(153); } +#endif -int board_init(void) +#ifdef CONFIG_ARCH_UNIPHIER_LD20 +static void uniphier_ld20_misc_init(void) { - led_puts("U0"); + sg_set_pinsel(149, 14, 8, 4); /* XIRQ0 -> XIRQ0 */ + sg_set_iectrl(149); + sg_set_pinsel(153, 14, 8, 4); /* XIRQ4 -> XIRQ4 */ + sg_set_iectrl(153); + + /* ES1 errata: increase VDD09 supply to suppress VBO noise */ + if (uniphier_get_soc_revision() == 1) { + writel(0x00000003, 0x6184e004); + writel(0x00000100, 0x6184e040); + writel(0x0000b500, 0x6184e024); + writel(0x00000001, 0x6184e000); + } + + cci500_init(2); +} +#endif + +struct uniphier_initdata { + enum uniphier_soc_id soc_id; + bool nand_2cs; + void (*pll_init)(void); + void (*clk_init)(void); + void (*misc_init)(void); +}; - switch (uniphier_get_soc_type()) { +struct uniphier_initdata uniphier_initdata[] = { #if defined(CONFIG_ARCH_UNIPHIER_SLD3) - case SOC_UNIPHIER_SLD3: - uniphier_nand_pin_init(true); - led_puts("U1"); - uniphier_sld3_pll_init(); - uniphier_ld4_clk_init(); - break; + { + .soc_id = SOC_UNIPHIER_SLD3, + .nand_2cs = true, + .pll_init = uniphier_sld3_pll_init, + .clk_init = uniphier_ld4_clk_init, + }, #endif #if defined(CONFIG_ARCH_UNIPHIER_LD4) - case SOC_UNIPHIER_LD4: - uniphier_nand_pin_init(true); - led_puts("U1"); - uniphier_ld4_pll_init(); - uniphier_ld4_clk_init(); - break; + { + .soc_id = SOC_UNIPHIER_LD4, + .nand_2cs = true, + .pll_init = uniphier_ld4_pll_init, + .clk_init = uniphier_ld4_clk_init, + }, #endif #if defined(CONFIG_ARCH_UNIPHIER_PRO4) - case SOC_UNIPHIER_PRO4: - uniphier_nand_pin_init(false); - led_puts("U1"); - uniphier_pro4_pll_init(); - uniphier_pro4_clk_init(); - break; + { + .soc_id = SOC_UNIPHIER_PRO4, + .nand_2cs = false, + .pll_init = uniphier_pro4_pll_init, + .clk_init = uniphier_pro4_clk_init, + }, #endif #if defined(CONFIG_ARCH_UNIPHIER_SLD8) - case SOC_UNIPHIER_SLD8: - uniphier_nand_pin_init(true); - led_puts("U1"); - uniphier_ld4_pll_init(); - uniphier_ld4_clk_init(); - break; + { + .soc_id = SOC_UNIPHIER_SLD8, + .nand_2cs = true, + .pll_init = uniphier_ld4_pll_init, + .clk_init = uniphier_ld4_clk_init, + }, #endif #if defined(CONFIG_ARCH_UNIPHIER_PRO5) - case SOC_UNIPHIER_PRO5: - uniphier_nand_pin_init(true); - led_puts("U1"); - uniphier_pro5_clk_init(); - break; + { + .soc_id = SOC_UNIPHIER_PRO5, + .nand_2cs = true, + .clk_init = uniphier_pro5_clk_init, + }, #endif #if defined(CONFIG_ARCH_UNIPHIER_PXS2) - case SOC_UNIPHIER_PXS2: - uniphier_nand_pin_init(true); - led_puts("U1"); - uniphier_pxs2_clk_init(); - break; + { + .soc_id = SOC_UNIPHIER_PXS2, + .nand_2cs = true, + .clk_init = uniphier_pxs2_clk_init, + }, #endif #if defined(CONFIG_ARCH_UNIPHIER_LD6B) - case SOC_UNIPHIER_LD6B: - uniphier_nand_pin_init(true); - led_puts("U1"); - uniphier_pxs2_clk_init(); - break; + { + .soc_id = SOC_UNIPHIER_LD6B, + .nand_2cs = true, + .clk_init = uniphier_pxs2_clk_init, + }, #endif #if defined(CONFIG_ARCH_UNIPHIER_LD11) - case SOC_UNIPHIER_LD11: - uniphier_nand_pin_init(false); - sg_set_pinsel(149, 14, 8, 4); /* XIRQ0 -> XIRQ0 */ - sg_set_iectrl(149); - sg_set_pinsel(153, 14, 8, 4); /* XIRQ4 -> XIRQ4 */ - sg_set_iectrl(153); - led_puts("U1"); - uniphier_ld11_pll_init(); - uniphier_ld11_clk_init(); - break; + { + .soc_id = SOC_UNIPHIER_LD11, + .nand_2cs = false, + .pll_init = uniphier_ld11_pll_init, + .clk_init = uniphier_ld11_clk_init, + .misc_init = uniphier_ld11_misc_init, + }, #endif #if defined(CONFIG_ARCH_UNIPHIER_LD20) - case SOC_UNIPHIER_LD20: - /* ES1 errata: increase VDD09 supply to suppress VBO noise */ - if (uniphier_get_soc_revision() == 1) { - writel(0x00000003, 0x6184e004); - writel(0x00000100, 0x6184e040); - writel(0x0000b500, 0x6184e024); - writel(0x00000001, 0x6184e000); - } - uniphier_nand_pin_init(false); - sg_set_pinsel(149, 14, 8, 4); /* XIRQ0 -> XIRQ0 */ - sg_set_iectrl(149); - sg_set_pinsel(153, 14, 8, 4); /* XIRQ4 -> XIRQ4 */ - sg_set_iectrl(153); - led_puts("U1"); - uniphier_ld20_pll_init(); - uniphier_ld20_clk_init(); - cci500_init(2); - break; + { + .soc_id = SOC_UNIPHIER_LD20, + .nand_2cs = false, + .pll_init = uniphier_ld20_pll_init, + .clk_init = uniphier_ld20_clk_init, + .misc_init = uniphier_ld20_misc_init, + }, #endif - default: - break; +}; + +static struct uniphier_initdata *uniphier_get_initdata( + enum uniphier_soc_id soc_id) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(uniphier_initdata); i++) { + if (uniphier_initdata[i].soc_id == soc_id) + return &uniphier_initdata[i]; } - uniphier_setup_xirq(); + return NULL; +} + +int board_init(void) +{ + struct uniphier_initdata *initdata; + enum uniphier_soc_id soc_id; + int ret; + + led_puts("U0"); + + soc_id = uniphier_get_soc_type(); + initdata = uniphier_get_initdata(soc_id); + if (!initdata) { + pr_err("unsupported board\n"); + return -EINVAL; + } + + if (IS_ENABLED(CONFIG_NAND_DENALI)) { + ret = uniphier_pin_init(initdata->nand_2cs ? + "nand2cs_grp" : "nand_grp"); + if (ret) + pr_err("failed to init NAND pins\n"); + } + + led_puts("U1"); + + if (initdata->pll_init) + initdata->pll_init(); led_puts("U2"); - support_card_late_init(); + initdata->clk_init(); led_puts("U3"); + if (initdata->misc_init) + initdata->misc_init(); + + led_puts("U4"); + + uniphier_setup_xirq(); + + led_puts("U5"); + + support_card_late_init(); + + led_puts("U6"); + #ifdef CONFIG_ARM64 uniphier_smp_kick_all_cpus(); #endif