From patchwork Sat Dec 3 05:06:08 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 86407 Delivered-To: patch@linaro.org Received: by 10.140.20.101 with SMTP id 92csp571228qgi; Fri, 2 Dec 2016 21:07:25 -0800 (PST) X-Received: by 10.28.88.18 with SMTP id m18mr499869wmb.26.1480741645236; Fri, 02 Dec 2016 21:07:25 -0800 (PST) Return-Path: Received: from theia.denx.de (theia.denx.de. [85.214.87.163]) by mx.google.com with ESMTP id g66si5575566wmf.113.2016.12.02.21.07.24; Fri, 02 Dec 2016 21:07:25 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) client-ip=85.214.87.163; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@google.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE dis=NONE) header.from=chromium.org Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4833AB3839; Sat, 3 Dec 2016 06:07:11 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id YOD8e40jKsNV; Sat, 3 Dec 2016 06:07:11 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 30399B38A1; Sat, 3 Dec 2016 06:06:43 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B33D7B3850 for ; Sat, 3 Dec 2016 06:06:29 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id KO3T1bkx3kus for ; Sat, 3 Dec 2016 06:06:29 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-oi0-f41.google.com (mail-oi0-f41.google.com [209.85.218.41]) by theia.denx.de (Postfix) with ESMTPS id 1B565A7624 for ; Sat, 3 Dec 2016 06:06:26 +0100 (CET) Received: by mail-oi0-f41.google.com with SMTP id v84so287948357oie.3 for ; Fri, 02 Dec 2016 21:06:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=MaCMD0kE1/9BIgMWiCf3mRZ/uwI1mSj+wmHq05Cy1eU=; b=Gzmfowuw+jLji7rwkMUcPxAIo6qNZR5j4r7Hf4A1T0V/V0rJ8Tc9l4ZMJ2FvPFngUn xfmq4Yc45v5nldYCkXtLDpeRuf1YVQn0FQLrYl5dlcJissAnGnClJbAB+oO191KUHvls e39zexJIsahbXoPacjqIuDCEa3P05Wizr7hnRfCR+SSNRJg+udZT1+WzZOMxQXo+6r6l ensHSUITEqcI8XnYhV/XGGvLu/FLrKhMavuzmmpZgfro/MhH8DC3GZchShDMpsDpNWBM qE9nCh0lwZr4nkwTAOgwExuIChkqSAbcLjcFi938L7Iw0+uqT1S8mz/wErSH2LcqiuFc +08w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=MaCMD0kE1/9BIgMWiCf3mRZ/uwI1mSj+wmHq05Cy1eU=; b=irBgeBIGXzp4ZIDdVsaOK7hu1oMKpFLaLBn630AFYxwgCmn15p6ZBMBEETJyReBRek ZKk+wgUyx1ShJaq1nPzl8iEfA7Ic01J0lpdOZjXm8gMWALqCDlIDlDbRazoSAVn02fRb 3EChL2xNJY1bIFJQCnyejIaT9RZdhFgCFjlWyv9OzMnZnfvklEY/g72Z62Z+EZ5ZhHZH F55k7Asw3OMy/yy4dqDJgLxU8G/4iy1OWC6xcEmwBcBoZT3jrgLP3g8tynl97bw6BNHT tLoL857bd5sSVAYHm2k6LuiEPrAwaIG97EQps4LBqmXrgpaVYOatOOGCdzHaiA8ewYT3 efdw== X-Gm-Message-State: AKaTC01rxZvYRx7zH63ViTr3Be2PLgkRAILz9goMu16/3fB52lb8fqTcQQgO0n2k0NojIKwP X-Received: by 10.202.89.197 with SMTP id n188mr25492336oib.156.1480741585182; Fri, 02 Dec 2016 21:06:25 -0800 (PST) Received: from kaki.bld.corp.google.com ([100.100.197.48]) by smtp.gmail.com with ESMTPSA id t42sm2724878ota.24.2016.12.02.21.06.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 02 Dec 2016 21:06:24 -0800 (PST) Received: by kaki.bld.corp.google.com (Postfix, from userid 121222) id 37B18428B3; Fri, 2 Dec 2016 22:06:24 -0700 (MST) From: Simon Glass To: U-Boot Mailing List Date: Fri, 2 Dec 2016 22:06:08 -0700 Message-Id: <1480741572-13582-6-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 2.8.0.rc3.226.g39d4020 In-Reply-To: <1480741572-13582-1-git-send-email-sjg@chromium.org> References: <1480741572-13582-1-git-send-email-sjg@chromium.org> Cc: Joe Hershberger , Jeffy Chen , huang lin Subject: [U-Boot] [PATCH v4 5/9] net: gmac_rk3288: Add RK3288 GMAC driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Sjoerd Simons Add a new driver for the GMAC ethernet interface present in Rockchip RK3288 SOCs. This driver subclasses the generic design-ware driver to add the glue needed specifically for Rockchip. Signed-off-by: Sjoerd Simons Signed-off-by: Simon Glass Acked-by: Joe Hershberger --- Changes in v4: None Changes in v3: - Add comments for struct gmac_rk3288_platdata - Adjust binding to use r/tx-delay instead of r/tx_delay - Sort includes - Use debug() instead of printf() for error - Use function calls instead of fix_mac_speed() hook - Use new clk interface Changes in v2: - Adjust to new hook name - Fix various coding style nits drivers/net/Kconfig | 7 +++ drivers/net/Makefile | 1 + drivers/net/gmac_rk3288.c | 154 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 162 insertions(+) create mode 100644 drivers/net/gmac_rk3288.c -- 2.8.0.rc3.226.g39d4020 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index f25d3ff..0027a2e 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -215,4 +215,11 @@ config PIC32_ETH This driver implements 10/100 Mbps Ethernet and MAC layer for Microchip PIC32 microcontrollers. +config GMAC_RK3288 + bool "Rockchip RK3288 Synopsys Designware Ethernet MAC" + depends on DM_ETH && ETH_DESIGNWARE + help + This driver provides Rockchip RK3288 network support based on the + Synopsys Designware driver. + endif # NETDEVICES diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 9a7bfc6..348e98b 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_FTGMAC100) += ftgmac100.o obj-$(CONFIG_FTMAC110) += ftmac110.o obj-$(CONFIG_FTMAC100) += ftmac100.o obj-$(CONFIG_GRETH) += greth.o +obj-$(CONFIG_GMAC_RK3288) += gmac_rk3288.o obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o obj-$(CONFIG_LAN91C96) += lan91c96.o diff --git a/drivers/net/gmac_rk3288.c b/drivers/net/gmac_rk3288.c new file mode 100644 index 0000000..0c22756 --- /dev/null +++ b/drivers/net/gmac_rk3288.c @@ -0,0 +1,154 @@ +/* + * (C) Copyright 2015 Sjoerd Simons + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Rockchip GMAC ethernet IP driver for U-Boot + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "designware.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Platform data for the gmac + * + * dw_eth_pdata: Required platform data for designware driver (must be first) + */ +struct gmac_rk3288_platdata { + struct dw_eth_pdata dw_eth_pdata; + int tx_delay; + int rx_delay; +}; + +static int gmac_rk3288_ofdata_to_platdata(struct udevice *dev) +{ + struct gmac_rk3288_platdata *pdata = dev_get_platdata(dev); + + pdata->tx_delay = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "tx-delay", 0x30); + pdata->rx_delay = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "rx-delay", 0x10); + + return designware_eth_ofdata_to_platdata(dev); +} + +static int gmac_rk3288_fix_mac_speed(struct dw_eth_dev *priv) +{ + struct rk3288_grf *grf; + int clk; + + switch (priv->phydev->speed) { + case 10: + clk = GMAC_CLK_SEL_2_5M; + break; + case 100: + clk = GMAC_CLK_SEL_25M; + break; + case 1000: + clk = GMAC_CLK_SEL_125M; + break; + default: + debug("Unknown phy speed: %d\n", priv->phydev->speed); + return -EINVAL; + } + + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + rk_clrsetreg(&grf->soc_con1, + GMAC_CLK_SEL_MASK << GMAC_CLK_SEL_SHIFT, + clk << GMAC_CLK_SEL_SHIFT); + + return 0; +} + +static int gmac_rk3288_probe(struct udevice *dev) +{ + struct gmac_rk3288_platdata *pdata = dev_get_platdata(dev); + struct rk3288_grf *grf; + struct clk clk; + int ret; + + ret = clk_get_by_index(dev, 0, &clk); + if (ret) + return ret; + + /* Since mac_clk is fed by an external clock we can use 0 here */ + ret = clk_set_rate(&clk, 0); + if (ret) + return ret; + + /* Set to RGMII mode */ + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + rk_clrsetreg(&grf->soc_con1, + RMII_MODE_MASK << RMII_MODE_SHIFT | + GMAC_PHY_INTF_SEL_MASK << GMAC_PHY_INTF_SEL_SHIFT, + GMAC_PHY_INTF_SEL_RGMII << GMAC_PHY_INTF_SEL_SHIFT); + + rk_clrsetreg(&grf->soc_con3, + RXCLK_DLY_ENA_GMAC_MASK << RXCLK_DLY_ENA_GMAC_SHIFT | + TXCLK_DLY_ENA_GMAC_MASK << TXCLK_DLY_ENA_GMAC_SHIFT | + CLK_RX_DL_CFG_GMAC_MASK << CLK_RX_DL_CFG_GMAC_SHIFT | + CLK_TX_DL_CFG_GMAC_MASK << CLK_TX_DL_CFG_GMAC_SHIFT, + RXCLK_DLY_ENA_GMAC_ENABLE << RXCLK_DLY_ENA_GMAC_SHIFT | + TXCLK_DLY_ENA_GMAC_ENABLE << TXCLK_DLY_ENA_GMAC_SHIFT | + pdata->rx_delay << CLK_RX_DL_CFG_GMAC_SHIFT | + pdata->tx_delay << CLK_TX_DL_CFG_GMAC_SHIFT); + + return designware_eth_probe(dev); +} + +static int gmac_rk3288_eth_start(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct dw_eth_dev *priv = dev_get_priv(dev); + int ret; + + ret = designware_eth_init(priv, pdata->enetaddr); + if (ret) + return ret; + ret = gmac_rk3288_fix_mac_speed(priv); + if (ret) + return ret; + ret = designware_eth_enable(priv); + if (ret) + return ret; + + return 0; +} + +const struct eth_ops gmac_rk3288_eth_ops = { + .start = gmac_rk3288_eth_start, + .send = designware_eth_send, + .recv = designware_eth_recv, + .free_pkt = designware_eth_free_pkt, + .stop = designware_eth_stop, + .write_hwaddr = designware_eth_write_hwaddr, +}; + +static const struct udevice_id rk3288_gmac_ids[] = { + { .compatible = "rockchip,rk3288-gmac" }, + { } +}; + +U_BOOT_DRIVER(eth_gmac_rk3288) = { + .name = "gmac_rk3288", + .id = UCLASS_ETH, + .of_match = rk3288_gmac_ids, + .ofdata_to_platdata = gmac_rk3288_ofdata_to_platdata, + .probe = gmac_rk3288_probe, + .ops = &gmac_rk3288_eth_ops, + .priv_auto_alloc_size = sizeof(struct dw_eth_dev), + .platdata_auto_alloc_size = sizeof(struct gmac_rk3288_platdata), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +};