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[85.214.87.163]) by mx.google.com with ESMTP id qu19si68563134wjb.286.2016.12.01.04.14.13; Thu, 01 Dec 2016 04:14:13 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) client-ip=85.214.87.163; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@baylibre-com.20150623.gappssmtp.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0F702B384B; Thu, 1 Dec 2016 13:13:05 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id XJzoNV5IcjqA; Thu, 1 Dec 2016 13:13:04 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 93D0BB38BC; Thu, 1 Dec 2016 13:12:33 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7CE6AA7580 for ; Thu, 1 Dec 2016 12:07:58 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id KFxbE3gfSGpb for ; Thu, 1 Dec 2016 12:07:58 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-wm0-f52.google.com (mail-wm0-f52.google.com [74.125.82.52]) by theia.denx.de (Postfix) with ESMTPS id 313A3A7576 for ; Thu, 1 Dec 2016 12:07:54 +0100 (CET) Received: by mail-wm0-f52.google.com with SMTP id t79so244039167wmt.0 for ; Thu, 01 Dec 2016 03:07:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id; bh=we0zeHLq+vWd/wS9cYMcXjzzNotx72OOGOBv7VpUFQQ=; b=PwA91fXfoho896oaa41bXvrKHYpiHJtuEl//QJKqDq7byxkLMOK74Wa/bUylWttVye uvdUMwRwvGf3VWeDiSZc9nLa6+IfpGZNk5VQf7Kn0eaPwiBfkeNnHyHgXWBR+5RUuoFi tOmzuGk2o89C/4ZAVucQ/ZSJJVC3+kZeA5gPmR0paAesbGjq0K7ss+RXrjxLN+sEAdW5 GFK7JS+z090bsiBmI+7ey63jXnkVBImoXF2FfCgki60UBdI/qoSbK9f7k6DfqIwohWRA WO+wKfrpy/lcTfg/bB8S1SSJFx0od2MS3dKB5PnTV77+g99m+HQD2+nyxsY3OtidfUte 8UAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=we0zeHLq+vWd/wS9cYMcXjzzNotx72OOGOBv7VpUFQQ=; b=JgI/fFnVsDEIENH5+X85kpxuDNcWpAFf9N/nMgQyiFvqToaK0/WZeXcypdavsMUUm4 6Lf3vOhWw9/R/VKBOrcruFv6ugd5ZaDywqC3+/9DoAwoMXONOwjDw282AD1kDuslRdhn BmyhXixBqIDPrGEXRJuMsBV+eHkPXG00jphmtq2Dqw+I34JN532dv8h8uDs8DJeEuTD5 8HtStXIgk8QvVxkuqhWdyiIDpKnWYbVYKXdMaa5TzlinXG99xDyQGMcEQ2SkkfCxilQX v67LxQgzRdOvfnJskHDkSjHQUSitD14Lb5yuY8q27+cPuxGqhb3pDkQLVPnmKCjVXED8 oFQQ== X-Gm-Message-State: AKaTC00ZA4qvq35VG/xlO5deHsrO+Athe6UKrjvzRZFMBuYe9w5OOkgToVTohFxj5EJ6Wm5H X-Received: by 10.28.26.80 with SMTP id a77mr30708600wma.31.1480590473707; Thu, 01 Dec 2016 03:07:53 -0800 (PST) Received: from localhost.localdomain ([90.63.244.31]) by smtp.gmail.com with ESMTPSA id k11sm288126wmb.18.2016.12.01.03.07.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 01 Dec 2016 03:07:53 -0800 (PST) From: Bartosz Golaszewski To: Kevin Hilman , Michael Turquette , Fabien Parent , Simon Glass , Heiko Schocher , Sekhar Nori Date: Thu, 1 Dec 2016 12:07:43 +0100 Message-Id: <1480590463-31252-1-git-send-email-bgolaszewski@baylibre.com> X-Mailer: git-send-email 2.1.4 X-Mailman-Approved-At: Thu, 01 Dec 2016 13:12:06 +0100 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH] davinci: omapl138_lcdk: increase PLL0 frequency X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The LCDC controller on the lcdk board has high memory throughput requirements. Even with the kernel-side tweaks to master peripheral and peripheral bus burst priorities, the default PLL0 frquency of 300 MHz is not enough to service the LCD controller and causes DMA FIFO underflows. Increment the PLL0 multiplier to 37, resulting in PLL0 frequency of 456 MHz - the same value that downstream reference u-boot from Texas Instruments uses. Signed-off-by: Bartosz Golaszewski --- include/configs/omapl138_lcdk.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.9.3 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot Reviewed-by: Tom Rini diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index f751fe7..18abac0 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -75,7 +75,7 @@ #define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001 #define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8003 -#define CONFIG_SYS_DA850_PLL0_PLLM 24 +#define CONFIG_SYS_DA850_PLL0_PLLM 37 #define CONFIG_SYS_DA850_PLL1_PLLM 21 /*