From patchwork Wed Oct 12 12:14:38 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 77552 Delivered-To: patch@linaro.org Received: by 10.140.97.247 with SMTP id m110csp417459qge; Wed, 12 Oct 2016 05:12:42 -0700 (PDT) X-Received: by 10.194.20.231 with SMTP id q7mr1041489wje.57.1476274362714; Wed, 12 Oct 2016 05:12:42 -0700 (PDT) Return-Path: Received: from theia.denx.de (theia.denx.de. [85.214.87.163]) by mx.google.com with ESMTP id dd4si10025049wjb.54.2016.10.12.05.12.42; Wed, 12 Oct 2016 05:12:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) client-ip=85.214.87.163; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C24FFA761E; Wed, 12 Oct 2016 14:12:41 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id x3_z2UgciMFz; Wed, 12 Oct 2016 14:12:41 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 21C36A75F0; Wed, 12 Oct 2016 14:12:41 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5D1B3A75F0 for ; Wed, 12 Oct 2016 14:12:37 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id tqSuzf_r4c6f for ; Wed, 12 Oct 2016 14:12:37 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from conuserg-12.nifty.com (conuserg-12.nifty.com [210.131.2.79]) by theia.denx.de (Postfix) with ESMTPS id A1A30A7537 for ; Wed, 12 Oct 2016 14:12:32 +0200 (CEST) Received: from beagle.diag.org (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-12.nifty.com with ESMTP id u9CCCCKi026267; Wed, 12 Oct 2016 21:12:13 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-12.nifty.com u9CCCCKi026267 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1476274333; bh=e5S+yjRSVocvryJAnOqilVX63TEmpC0NQybUq8ba8ew=; h=From:To:Cc:Subject:Date:From; b=2zZdLac0Xq4WhzAGfN9yhe6L1fbNuZED0wn2j9fcMKzth0VRYK8424f0Pk6018lTy e2EzYxllr4e8eo62HlzjXZM7vnwxjcT8yAgmfjLlhFIBHM7CYTqnVS1LI1xBQOxCVN R2Awp5AKzd4tBAIIpQB1bhZsKSj1BBR/orT989gBBzapFQuOxrFkrr9+noQGqyFOA8 OSMh6HOVdiwqcJaWUadPm1uWI9GzLsADsOZ9QowHx0dBPqWBHFA+6/2LEil1ZVR9vV nhW5zQt6KlnfXeDO3SPNeidGe6zkp7DfEBvpjC5fWiiYtcdWJy+DZoBgg6RVmCTqwt ariE/q8vyKkow== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Wed, 12 Oct 2016 21:14:38 +0900 Message-Id: <1476274479-7533-1-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 1.9.1 Cc: Albert Aribaud Subject: [U-Boot] [PATCH] ARM: uniphier: fix addresses of Cortex-A72 gear setting macros X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" My mistake during copy-paste work. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/sc64-regs.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -- 1.9.1 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot diff --git a/arch/arm/mach-uniphier/sc64-regs.h b/arch/arm/mach-uniphier/sc64-regs.h index 780fdd1..b0a4281 100644 --- a/arch/arm/mach-uniphier/sc64-regs.h +++ b/arch/arm/mach-uniphier/sc64-regs.h @@ -63,9 +63,9 @@ #define SC_CLKCTRL7_UMC31 (1 << 1) #define SC_CLKCTRL7_UMC30 (1 << 0) -#define SC_CA72_GEARST (SC_BASE_ADDR | 0x8080) -#define SC_CA72_GEARSET (SC_BASE_ADDR | 0x8084) -#define SC_CA72_GEARUPD (SC_BASE_ADDR | 0x8088) +#define SC_CA72_GEARST (SC_BASE_ADDR | 0x8000) +#define SC_CA72_GEARSET (SC_BASE_ADDR | 0x8004) +#define SC_CA72_GEARUPD (SC_BASE_ADDR | 0x8008) #define SC_CA53_GEARST (SC_BASE_ADDR | 0x8080) #define SC_CA53_GEARSET (SC_BASE_ADDR | 0x8084) #define SC_CA53_GEARUPD (SC_BASE_ADDR | 0x8088)