From patchwork Wed Aug 10 07:08:39 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 73604 Delivered-To: patch@linaro.org Received: by 10.140.29.52 with SMTP id a49csp264893qga; Wed, 10 Aug 2016 00:26:27 -0700 (PDT) X-Received: by 10.28.92.71 with SMTP id q68mr1499244wmb.85.1470813987303; Wed, 10 Aug 2016 00:26:27 -0700 (PDT) Return-Path: Received: from theia.denx.de (theia.denx.de. [85.214.87.163]) by mx.google.com with ESMTP id z13si38579738wjr.64.2016.08.10.00.26.27; Wed, 10 Aug 2016 00:26:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) client-ip=85.214.87.163; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 68329A7553; Wed, 10 Aug 2016 09:26:21 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id znVZo7DXRbSC; Wed, 10 Aug 2016 09:26:21 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 736A8A754C; Wed, 10 Aug 2016 09:19:51 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0B5974B97D for ; Wed, 10 Aug 2016 09:07:43 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id aEFRdLsbHdGH for ; Wed, 10 Aug 2016 09:07:42 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from conuserg-11.nifty.com (conuserg-11.nifty.com [210.131.2.78]) by theia.denx.de (Postfix) with ESMTPS id 9D57CA7532 for ; Wed, 10 Aug 2016 09:07:23 +0200 (CEST) Received: from beagle.diag.org (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-11.nifty.com with ESMTP id u7A76xSp005792; Wed, 10 Aug 2016 16:07:01 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-11.nifty.com u7A76xSp005792 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1470812821; bh=q7islJQWUERiyqDJ4LFg4pM+G7dWJWGvuSL/U79kvDI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IBdlPvlGXyZkcdeg0sEmVK4PyPpgMNeZo17ZVFfYuNvo013lhbnBcqR5ei5dW/jbk +so0dy73FIMeOvbQy5mHq4FBu6KGysZrs+dpIo3Sw9hP6x7EccWy8HrUViyUCDkQll /45jMSzGlw4enE+pXun3xjobCo9H5s/4PvwdfBfAncvbvkn2d5zXsIXG+y//TsdKGs cSQxOokXvhwub2Dl8783sN25TBGS3LAIrhIia9xTTxF4qPf42UTLZvdjQSvrxY5ZGT tQ3mfP2GlADZoJ0ltoWCDnoUheoMPV8MSR1UtZr35SoLHjQfxWFIw2lZ6b4E6vPkoR V/ypoTUrvSSjQ== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Wed, 10 Aug 2016 16:08:39 +0900 Message-Id: <1470812929-21178-5-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1470812929-21178-1-git-send-email-yamada.masahiro@socionext.com> References: <1470812929-21178-1-git-send-email-yamada.masahiro@socionext.com> Subject: [U-Boot] [PATCH 04/14] ARM: uniphier: refactor L2 zero-touching code in lowlevel_init X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Here, the ldr pseudo-instruction falls into the ldr + data set. The register access by [r1, #offset] produces shorter code. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/arm32/lowlevel_init.S | 48 +++++++++++++--------------- 1 file changed, 22 insertions(+), 26 deletions(-) -- 1.9.1 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot diff --git a/arch/arm/mach-uniphier/arm32/lowlevel_init.S b/arch/arm/mach-uniphier/arm32/lowlevel_init.S index 8e32b35..2be9505 100644 --- a/arch/arm/mach-uniphier/arm32/lowlevel_init.S +++ b/arch/arm/mach-uniphier/arm32/lowlevel_init.S @@ -11,8 +11,6 @@ #include #include -#include "ssc-regs.h" - ENTRY(lowlevel_init) mov r8, lr @ persevere link reg across call @@ -88,39 +86,37 @@ ENDPROC(enable_mmu) */ #define BOOT_RAM_SIZE (SZ_32K) #define BOOT_RAM_BASE ((CONFIG_SPL_STACK) - (BOOT_RAM_SIZE)) -#define BOOT_WAY_BITS (0x00000100) /* way 8 */ +#define BOOT_RAM_WAYS (0x00000100) @ way 8 + +#define SSCO_BASE 0x506c0000 +#define SSCOPE 0x244 +#define SSCOQM 0x248 +#define SSCOQAD 0x24c +#define SSCOQSZ 0x250 +#define SSCOQWN 0x258 +#define SSCOPPQSEF 0x25c +#define SSCOLPQS 0x260 ENTRY(setup_init_ram) - /* - * Touch to zero for the boot way - */ -0: - /* - * set UNIPHIER_SSCOQM, UNIPHIER_SSCOQAD, UNIPHIER_SSCOQSZ, UNIPHIER_SSCOQWN in this order - */ - ldr r0, = 0x00408006 @ touch to zero with address range - ldr r1, = UNIPHIER_SSCOQM - str r0, [r1] + ldr r1, = SSCO_BASE + + /* Touch to zero for the boot way */ +0: ldr r0, = 0x00408006 @ touch to zero with address range + str r0, [r1, #SSCOQM] ldr r0, = BOOT_RAM_BASE - ldr r1, = UNIPHIER_SSCOQAD - str r0, [r1] + str r0, [r1, #SSCOQAD] ldr r0, = BOOT_RAM_SIZE - ldr r1, = UNIPHIER_SSCOQSZ - str r0, [r1] - ldr r0, = BOOT_WAY_BITS - ldr r1, = UNIPHIER_SSCOQWN - str r0, [r1] - ldr r1, = UNIPHIER_SSCOPPQSEF - ldr r0, [r1] + str r0, [r1, #SSCOQSZ] + ldr r0, = BOOT_RAM_WAYS + str r0, [r1, #SSCOQWN] + ldr r0, [r1, #SSCOPPQSEF] cmp r0, #0 @ check if the command is successfully set bne 0b @ try again if an error occurs - ldr r1, = UNIPHIER_SSCOLPQS -1: - ldr r0, [r1] +1: ldr r0, [r1, #SSCOLPQS] cmp r0, #0x4 bne 1b @ wait until the operation is completed - str r0, [r1] @ clear the complete notification flag + str r0, [r1, #SSCOLPQS] @ clear the complete notification flag mov pc, lr ENDPROC(setup_init_ram)