From patchwork Wed Aug 10 07:08:37 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 73609 Delivered-To: patch@linaro.org Received: by 10.140.29.52 with SMTP id a49csp267057qga; Wed, 10 Aug 2016 00:33:10 -0700 (PDT) X-Received: by 10.28.185.202 with SMTP id j193mr1712825wmf.78.1470814390282; Wed, 10 Aug 2016 00:33:10 -0700 (PDT) Return-Path: Received: from theia.denx.de (theia.denx.de. [85.214.87.163]) by mx.google.com with ESMTP id j6si6777695wmj.88.2016.08.10.00.33.09; Wed, 10 Aug 2016 00:33:10 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) client-ip=85.214.87.163; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6D0824B71E; Wed, 10 Aug 2016 09:33:05 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id RQ9ORZsCZPOu; Wed, 10 Aug 2016 09:33:04 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7891AA7558; Wed, 10 Aug 2016 09:25:49 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 766F0A750A for ; Wed, 10 Aug 2016 09:07:44 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id dRs-k42pb0CO for ; Wed, 10 Aug 2016 09:07:44 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from conuserg-11.nifty.com (conuserg-11.nifty.com [210.131.2.78]) by theia.denx.de (Postfix) with ESMTPS id 5DE26A7533 for ; Wed, 10 Aug 2016 09:07:21 +0200 (CEST) Received: from beagle.diag.org (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-11.nifty.com with ESMTP id u7A76xSn005792; Wed, 10 Aug 2016 16:07:00 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-11.nifty.com u7A76xSn005792 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1470812820; bh=DyLchY6mSAVb474RX0k69RO38T7w1nNbZjZw2W1pyMU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NehuRWN0LTCLJcm8CJpTE+ogdRSZg2k7F9V3AQmDviuNzpeIA3XCgFQwuhCcJ7Y+X Eb7bjxjYAMMqlRgt8rQHpawCjXJG4AMI4TcHFTk8wMpRNZN7wUkt8bVr54lvODYGtS KevrjH/Nbov/BTdEs72fKaToDkjsedwgLJQq1m0g2v6RzcD0WQIIiAs5prhczQBl5g Tr8aMplR3l/6ble4hYys/Q1ianqvhJ6LrorHyqTIKBUxiXoCzzDgVc9MNaMh03ql8Z Q6ako2iuShLXD3tH6eDkER4RGWUnOyHMsouo28oz2nCnsfDa9qq7JbOIxIx+ypyzBI I1otxzM4gqhvg== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Wed, 10 Aug 2016 16:08:37 +0900 Message-Id: <1470812929-21178-3-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1470812929-21178-1-git-send-email-yamada.masahiro@socionext.com> References: <1470812929-21178-1-git-send-email-yamada.masahiro@socionext.com> Subject: [U-Boot] [PATCH 02/14] ARM: uniphier: support prefetch and touch operations for outer cache X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The UniPhier outer cache (L2 cache on ARMv7 SoCs) can be used as SRAM by locking ways. These functions will be used to transfer the trampoline code for SMP into the locked SRAM. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/arm32/cache-uniphier.c | 50 +++++++++++++++++++++------ arch/arm/mach-uniphier/arm32/cache-uniphier.h | 17 +++++++++ 2 files changed, 57 insertions(+), 10 deletions(-) create mode 100644 arch/arm/mach-uniphier/arm32/cache-uniphier.h -- 1.9.1 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot diff --git a/arch/arm/mach-uniphier/arm32/cache-uniphier.c b/arch/arm/mach-uniphier/arm32/cache-uniphier.c index 7b126bb..a210835 100644 --- a/arch/arm/mach-uniphier/arm32/cache-uniphier.c +++ b/arch/arm/mach-uniphier/arm32/cache-uniphier.c @@ -12,12 +12,13 @@ #include #include +#include "cache-uniphier.h" #include "ssc-regs.h" #define UNIPHIER_SSCOQAD_IS_NEEDED(op) \ ((op & UNIPHIER_SSCOQM_S_MASK) == UNIPHIER_SSCOQM_S_RANGE) - -#ifdef CONFIG_UNIPHIER_L2CACHE_ON +#define UNIPHIER_SSCOQWM_IS_NEEDED(op) \ + ((op & UNIPHIER_SSCOQM_TID_MASK) == UNIPHIER_SSCOQM_TID_WAY) /* uniphier_cache_sync - perform a sync point for a particular cache level */ static void uniphier_cache_sync(void) @@ -33,9 +34,11 @@ static void uniphier_cache_sync(void) * * @start: start address of range operation (don't care for "all" operation) * @size: data size of range operation (don't care for "all" operation) + * @ways: target ways (don't care for operations other than pre-fetch, touch * @operation: flags to specify the desired cache operation */ -static void uniphier_cache_maint_common(u32 start, u32 size, u32 operation) +static void uniphier_cache_maint_common(u32 start, u32 size, u32 ways, + u32 operation) { /* clear the complete notification flag */ writel(UNIPHIER_SSCOLPQS_EF, UNIPHIER_SSCOLPQS); @@ -49,6 +52,10 @@ static void uniphier_cache_maint_common(u32 start, u32 size, u32 operation) writel(start, UNIPHIER_SSCOQAD); writel(size, UNIPHIER_SSCOQSZ); } + + /* set target ways if needed */ + if (unlikely(UNIPHIER_SSCOQWM_IS_NEEDED(operation))) + writel(ways, UNIPHIER_SSCOQWN); } while (unlikely(readl(UNIPHIER_SSCOPPQSEF) & (UNIPHIER_SSCOPPQSEF_FE | UNIPHIER_SSCOPPQSEF_OE))); @@ -59,12 +66,13 @@ static void uniphier_cache_maint_common(u32 start, u32 size, u32 operation) static void uniphier_cache_maint_all(u32 operation) { - uniphier_cache_maint_common(0, 0, UNIPHIER_SSCOQM_S_ALL | operation); + uniphier_cache_maint_common(0, 0, 0, UNIPHIER_SSCOQM_S_ALL | operation); uniphier_cache_sync(); } -static void uniphier_cache_maint_range(u32 start, u32 end, u32 operation) +static void uniphier_cache_maint_range(u32 start, u32 end, u32 ways, + u32 operation) { u32 size; @@ -91,7 +99,7 @@ static void uniphier_cache_maint_range(u32 start, u32 end, u32 operation) while (size) { u32 chunk_size = min_t(u32, size, UNIPHIER_SSC_RANGE_OP_MAX_SIZE); - uniphier_cache_maint_common(start, chunk_size, + uniphier_cache_maint_common(start, chunk_size, ways, UNIPHIER_SSCOQM_S_RANGE | operation); start += chunk_size; @@ -101,6 +109,28 @@ static void uniphier_cache_maint_range(u32 start, u32 end, u32 operation) uniphier_cache_sync(); } +void uniphier_cache_prefetch_range(u32 start, u32 end, u32 ways) +{ + uniphier_cache_maint_range(start, end, ways, + UNIPHIER_SSCOQM_TID_WAY | + UNIPHIER_SSCOQM_CM_PREFETCH); +} + +void uniphier_cache_touch_range(u32 start, u32 end, u32 ways) +{ + uniphier_cache_maint_range(start, end, ways, + UNIPHIER_SSCOQM_TID_WAY | + UNIPHIER_SSCOQM_CM_TOUCH); +} + +void uniphier_cache_touch_zero_range(u32 start, u32 end, u32 ways) +{ + uniphier_cache_maint_range(start, end, ways, + UNIPHIER_SSCOQM_TID_WAY | + UNIPHIER_SSCOQM_CM_TOUCH_ZERO); +} + +#ifdef CONFIG_UNIPHIER_L2CACHE_ON void v7_outer_cache_flush_all(void) { uniphier_cache_maint_all(UNIPHIER_SSCOQM_CM_FLUSH); @@ -113,14 +143,14 @@ void v7_outer_cache_inval_all(void) void v7_outer_cache_flush_range(u32 start, u32 end) { - uniphier_cache_maint_range(start, end, UNIPHIER_SSCOQM_CM_FLUSH); + uniphier_cache_maint_range(start, end, 0, UNIPHIER_SSCOQM_CM_FLUSH); } void v7_outer_cache_inval_range(u32 start, u32 end) { if (start & (UNIPHIER_SSC_LINE_SIZE - 1)) { start &= ~(UNIPHIER_SSC_LINE_SIZE - 1); - uniphier_cache_maint_range(start, UNIPHIER_SSC_LINE_SIZE, + uniphier_cache_maint_range(start, UNIPHIER_SSC_LINE_SIZE, 0, UNIPHIER_SSCOQM_CM_FLUSH); start += UNIPHIER_SSC_LINE_SIZE; } @@ -132,7 +162,7 @@ void v7_outer_cache_inval_range(u32 start, u32 end) if (end & (UNIPHIER_SSC_LINE_SIZE - 1)) { end &= ~(UNIPHIER_SSC_LINE_SIZE - 1); - uniphier_cache_maint_range(end, UNIPHIER_SSC_LINE_SIZE, + uniphier_cache_maint_range(end, UNIPHIER_SSC_LINE_SIZE, 0, UNIPHIER_SSCOQM_CM_FLUSH); } @@ -141,7 +171,7 @@ void v7_outer_cache_inval_range(u32 start, u32 end) return; } - uniphier_cache_maint_range(start, end, UNIPHIER_SSCOQM_CM_INV); + uniphier_cache_maint_range(start, end, 0, UNIPHIER_SSCOQM_CM_INV); } void v7_outer_cache_enable(void) diff --git a/arch/arm/mach-uniphier/arm32/cache-uniphier.h b/arch/arm/mach-uniphier/arm32/cache-uniphier.h new file mode 100644 index 0000000..f67f6ae --- /dev/null +++ b/arch/arm/mach-uniphier/arm32/cache-uniphier.h @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CACHE_UNIPHIER_H +#define __CACHE_UNIPHIER_H + +#include + +void uniphier_cache_prefetch_range(u32 start, u32 end, u32 ways); +void uniphier_cache_touch_range(u32 start, u32 end, u32 ways); +void uniphier_cache_touch_zero_range(u32 start, u32 end, u32 ways); + +#endif /* __CACHE_UNIPHIER_H */