From patchwork Wed Aug 10 07:08:44 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 73608 Delivered-To: patch@linaro.org Received: by 10.140.29.52 with SMTP id a49csp266584qga; Wed, 10 Aug 2016 00:31:50 -0700 (PDT) X-Received: by 10.194.104.106 with SMTP id gd10mr2806593wjb.55.1470814309998; Wed, 10 Aug 2016 00:31:49 -0700 (PDT) Return-Path: Received: from theia.denx.de (theia.denx.de. [85.214.87.163]) by mx.google.com with ESMTP id d77si6768890wmh.91.2016.08.10.00.31.49; Wed, 10 Aug 2016 00:31:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) client-ip=85.214.87.163; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 27877A7548; Wed, 10 Aug 2016 09:31:49 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id cOd546jN-bva; Wed, 10 Aug 2016 09:31:49 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id EA4E3A751C; Wed, 10 Aug 2016 09:24:31 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 19E044BDE9 for ; Wed, 10 Aug 2016 09:07:43 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id p8IfYXpH-FuJ for ; Wed, 10 Aug 2016 09:07:42 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from conuserg-11.nifty.com (conuserg-11.nifty.com [210.131.2.78]) by theia.denx.de (Postfix) with ESMTPS id CD78DA7518 for ; Wed, 10 Aug 2016 09:07:22 +0200 (CEST) Received: from beagle.diag.org (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-11.nifty.com with ESMTP id u7A76xSu005792; Wed, 10 Aug 2016 16:07:04 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-11.nifty.com u7A76xSu005792 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1470812824; bh=GYdxMk7zJ4HvrXl/O5+gs3LyZlQLHY6/sbcA5rRVxQo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=i2cVIJ8GAYC/tjgh3m38OntibwFjCRKGjseSfZKK3PXpYBaZT/qaoYbgQbuwLJM87 R0RTqiXpiG8VkydQxQXGUYy1kvaIYmSWobO3kLimsvqHNoJjdvQEjUSmRRCeoeEBnx m1bMDfQPPgsWZP2M+h5hYBQbJ+ZJXv72LGluZINbdzqinBe9pXd+nX8TffBBeaA0I3 UhkAgEgWK8NA53UJ6BHPXPPCJngaVLb7QORXuoVYLW3w+/9auwvQ8Ykv5MZKyJGZRI imPIVFY5zvqITy+nolRXCnmBWt6Pt6XIAjpbXLs1dm7ElZ+liZpTdVz9pifgsdpJxt di7AkBhYvdFMA== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Wed, 10 Aug 2016 16:08:44 +0900 Message-Id: <1470812929-21178-10-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1470812929-21178-1-git-send-email-yamada.masahiro@socionext.com> References: <1470812929-21178-1-git-send-email-yamada.masahiro@socionext.com> Subject: [U-Boot] [PATCH 09/14] ARM: uniphier: move outer cache register macros to .c file X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Now, all of these macros are only used in cache-uniphier.c, so there is no need to export them in a header file. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/arm32/cache-uniphier.c | 56 +++++++++++++++++++++- arch/arm/mach-uniphier/arm32/ssc-regs.h | 68 --------------------------- 2 files changed, 55 insertions(+), 69 deletions(-) delete mode 100644 arch/arm/mach-uniphier/arm32/ssc-regs.h -- 1.9.1 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot diff --git a/arch/arm/mach-uniphier/arm32/cache-uniphier.c b/arch/arm/mach-uniphier/arm32/cache-uniphier.c index 4bb7d95..77a0b78 100644 --- a/arch/arm/mach-uniphier/arm32/cache-uniphier.c +++ b/arch/arm/mach-uniphier/arm32/cache-uniphier.c @@ -13,7 +13,61 @@ #include #include "cache-uniphier.h" -#include "ssc-regs.h" + +/* control registers */ +#define UNIPHIER_SSCC 0x500c0000 /* Control Register */ +#define UNIPHIER_SSCC_BST (0x1 << 20) /* UCWG burst read */ +#define UNIPHIER_SSCC_ACT (0x1 << 19) /* Inst-Data separate */ +#define UNIPHIER_SSCC_WTG (0x1 << 18) /* WT gathering on */ +#define UNIPHIER_SSCC_PRD (0x1 << 17) /* enable pre-fetch */ +#define UNIPHIER_SSCC_ON (0x1 << 0) /* enable cache */ +#define UNIPHIER_SSCLPDAWCR 0x500c0030 /* Unified/Data Active Way Control */ +#define UNIPHIER_SSCLPIAWCR 0x500c0034 /* Instruction Active Way Control */ + +/* revision registers */ +#define UNIPHIER_SSCID 0x503c0100 /* ID Register */ + +/* operation registers */ +#define UNIPHIER_SSCOPE 0x506c0244 /* Cache Operation Primitive Entry */ +#define UNIPHIER_SSCOPE_CM_INV 0x0 /* invalidate */ +#define UNIPHIER_SSCOPE_CM_CLEAN 0x1 /* clean */ +#define UNIPHIER_SSCOPE_CM_FLUSH 0x2 /* flush */ +#define UNIPHIER_SSCOPE_CM_SYNC 0x8 /* sync (drain bufs) */ +#define UNIPHIER_SSCOPE_CM_FLUSH_PREFETCH 0x9 /* flush p-fetch buf */ +#define UNIPHIER_SSCOQM 0x506c0248 +#define UNIPHIER_SSCOQM_TID_MASK (0x3 << 21) +#define UNIPHIER_SSCOQM_TID_LRU_DATA (0x0 << 21) +#define UNIPHIER_SSCOQM_TID_LRU_INST (0x1 << 21) +#define UNIPHIER_SSCOQM_TID_WAY (0x2 << 21) +#define UNIPHIER_SSCOQM_S_MASK (0x3 << 17) +#define UNIPHIER_SSCOQM_S_RANGE (0x0 << 17) +#define UNIPHIER_SSCOQM_S_ALL (0x1 << 17) +#define UNIPHIER_SSCOQM_S_WAY (0x2 << 17) +#define UNIPHIER_SSCOQM_CE (0x1 << 15) /* notify completion */ +#define UNIPHIER_SSCOQM_CW (0x1 << 14) +#define UNIPHIER_SSCOQM_CM_MASK (0x7) +#define UNIPHIER_SSCOQM_CM_INV 0x0 /* invalidate */ +#define UNIPHIER_SSCOQM_CM_CLEAN 0x1 /* clean */ +#define UNIPHIER_SSCOQM_CM_FLUSH 0x2 /* flush */ +#define UNIPHIER_SSCOQM_CM_PREFETCH 0x3 /* prefetch to cache */ +#define UNIPHIER_SSCOQM_CM_PREFETCH_BUF 0x4 /* prefetch to pf-buf */ +#define UNIPHIER_SSCOQM_CM_TOUCH 0x5 /* touch */ +#define UNIPHIER_SSCOQM_CM_TOUCH_ZERO 0x6 /* touch to zero */ +#define UNIPHIER_SSCOQM_CM_TOUCH_DIRTY 0x7 /* touch with dirty */ +#define UNIPHIER_SSCOQAD 0x506c024c /* Cache Operation Queue Address */ +#define UNIPHIER_SSCOQSZ 0x506c0250 /* Cache Operation Queue Size */ +#define UNIPHIER_SSCOQMASK 0x506c0254 /* Cache Operation Queue Address Mask */ +#define UNIPHIER_SSCOQWN 0x506c0258 /* Cache Operation Queue Way Number */ +#define UNIPHIER_SSCOPPQSEF 0x506c025c /* Cache Operation Queue Set Complete */ +#define UNIPHIER_SSCOPPQSEF_FE (0x1 << 1) +#define UNIPHIER_SSCOPPQSEF_OE (0x1 << 0) +#define UNIPHIER_SSCOLPQS 0x506c0260 /* Cache Operation Queue Status */ +#define UNIPHIER_SSCOLPQS_EF (0x1 << 2) +#define UNIPHIER_SSCOLPQS_EST (0x1 << 1) +#define UNIPHIER_SSCOLPQS_QST (0x1 << 0) + +#define UNIPHIER_SSC_LINE_SIZE 128 +#define UNIPHIER_SSC_RANGE_OP_MAX_SIZE (0x00400000 - (UNIPHIER_SSC_LINE_SIZE)) #define UNIPHIER_SSCOQAD_IS_NEEDED(op) \ ((op & UNIPHIER_SSCOQM_S_MASK) == UNIPHIER_SSCOQM_S_RANGE) diff --git a/arch/arm/mach-uniphier/arm32/ssc-regs.h b/arch/arm/mach-uniphier/arm32/ssc-regs.h deleted file mode 100644 index 8f423e9..0000000 --- a/arch/arm/mach-uniphier/arm32/ssc-regs.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * UniPhier System Cache (L2 Cache) registers - * - * Copyright (C) 2011-2014 Panasonic Corporation - * Copyright (C) 2016 Socionext Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef ARCH_SSC_REGS_H -#define ARCH_SSC_REGS_H - -/* control registers */ -#define UNIPHIER_SSCC 0x500c0000 /* Control Register */ -#define UNIPHIER_SSCC_BST (0x1 << 20) /* UCWG burst read */ -#define UNIPHIER_SSCC_ACT (0x1 << 19) /* Inst-Data separate */ -#define UNIPHIER_SSCC_WTG (0x1 << 18) /* WT gathering on */ -#define UNIPHIER_SSCC_PRD (0x1 << 17) /* enable pre-fetch */ -#define UNIPHIER_SSCC_ON (0x1 << 0) /* enable cache */ -#define UNIPHIER_SSCLPDAWCR 0x500c0030 /* Unified/Data Active Way Control */ -#define UNIPHIER_SSCLPIAWCR 0x500c0034 /* Instruction Active Way Control */ - -/* revision registers */ -#define UNIPHIER_SSCID 0x503c0100 /* ID Register */ - -/* operation registers */ -#define UNIPHIER_SSCOPE 0x506c0244 /* Cache Operation Primitive Entry */ -#define UNIPHIER_SSCOPE_CM_INV 0x0 /* invalidate */ -#define UNIPHIER_SSCOPE_CM_CLEAN 0x1 /* clean */ -#define UNIPHIER_SSCOPE_CM_FLUSH 0x2 /* flush */ -#define UNIPHIER_SSCOPE_CM_SYNC 0x8 /* sync (drain bufs) */ -#define UNIPHIER_SSCOPE_CM_FLUSH_PREFETCH 0x9 /* flush p-fetch buf */ -#define UNIPHIER_SSCOQM 0x506c0248 -#define UNIPHIER_SSCOQM_TID_MASK (0x3 << 21) -#define UNIPHIER_SSCOQM_TID_LRU_DATA (0x0 << 21) -#define UNIPHIER_SSCOQM_TID_LRU_INST (0x1 << 21) -#define UNIPHIER_SSCOQM_TID_WAY (0x2 << 21) -#define UNIPHIER_SSCOQM_S_MASK (0x3 << 17) -#define UNIPHIER_SSCOQM_S_RANGE (0x0 << 17) -#define UNIPHIER_SSCOQM_S_ALL (0x1 << 17) -#define UNIPHIER_SSCOQM_S_WAY (0x2 << 17) -#define UNIPHIER_SSCOQM_CE (0x1 << 15) /* notify completion */ -#define UNIPHIER_SSCOQM_CW (0x1 << 14) -#define UNIPHIER_SSCOQM_CM_MASK (0x7) -#define UNIPHIER_SSCOQM_CM_INV 0x0 /* invalidate */ -#define UNIPHIER_SSCOQM_CM_CLEAN 0x1 /* clean */ -#define UNIPHIER_SSCOQM_CM_FLUSH 0x2 /* flush */ -#define UNIPHIER_SSCOQM_CM_PREFETCH 0x3 /* prefetch to cache */ -#define UNIPHIER_SSCOQM_CM_PREFETCH_BUF 0x4 /* prefetch to pf-buf */ -#define UNIPHIER_SSCOQM_CM_TOUCH 0x5 /* touch */ -#define UNIPHIER_SSCOQM_CM_TOUCH_ZERO 0x6 /* touch to zero */ -#define UNIPHIER_SSCOQM_CM_TOUCH_DIRTY 0x7 /* touch with dirty */ -#define UNIPHIER_SSCOQAD 0x506c024c /* Cache Operation Queue Address */ -#define UNIPHIER_SSCOQSZ 0x506c0250 /* Cache Operation Queue Size */ -#define UNIPHIER_SSCOQMASK 0x506c0254 /* Cache Operation Queue Address Mask */ -#define UNIPHIER_SSCOQWN 0x506c0258 /* Cache Operation Queue Way Number */ -#define UNIPHIER_SSCOPPQSEF 0x506c025c /* Cache Operation Queue Set Complete */ -#define UNIPHIER_SSCOPPQSEF_FE (0x1 << 1) -#define UNIPHIER_SSCOPPQSEF_OE (0x1 << 0) -#define UNIPHIER_SSCOLPQS 0x506c0260 /* Cache Operation Queue Status */ -#define UNIPHIER_SSCOLPQS_EF (0x1 << 2) -#define UNIPHIER_SSCOLPQS_EST (0x1 << 1) -#define UNIPHIER_SSCOLPQS_QST (0x1 << 0) - -#define UNIPHIER_SSC_LINE_SIZE 128 -#define UNIPHIER_SSC_RANGE_OP_MAX_SIZE (0x00400000 - (UNIPHIER_SSC_LINE_SIZE)) - -#endif /* ARCH_SSC_REGS_H */