From patchwork Fri Jul 22 11:20:11 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 72614 Delivered-To: patch@linaro.org Received: by 10.140.29.52 with SMTP id a49csp941659qga; Fri, 22 Jul 2016 04:19:05 -0700 (PDT) X-Received: by 10.194.144.33 with SMTP id sj1mr515910wjb.150.1469186345597; Fri, 22 Jul 2016 04:19:05 -0700 (PDT) Return-Path: Received: from theia.denx.de (theia.denx.de. [85.214.87.163]) by mx.google.com with ESMTP id q63si9573052wmd.131.2016.07.22.04.19.05; Fri, 22 Jul 2016 04:19:05 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) client-ip=85.214.87.163; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0EEC4A769C; Fri, 22 Jul 2016 13:19:04 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id vZ6bPMvVyHFt; Fri, 22 Jul 2016 13:19:03 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 575CFA7624; Fri, 22 Jul 2016 13:19:03 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C1E1DA7624 for ; Fri, 22 Jul 2016 13:18:59 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ypIadUKsKOj5 for ; Fri, 22 Jul 2016 13:18:59 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from conuserg-07.nifty.com (conuserg-07.nifty.com [210.131.2.74]) by theia.denx.de (Postfix) with ESMTPS id 103EBA75B4 for ; Fri, 22 Jul 2016 13:18:55 +0200 (CEST) Received: from beagle.diag.org (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-07.nifty.com with ESMTP id u6MBINie026096; Fri, 22 Jul 2016 20:18:24 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-07.nifty.com u6MBINie026096 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1469186304; bh=5tvYGbQZn00fB+Yz8C/5vYE3nOGuawfUuLnGEbED2JQ=; h=From:To:Cc:Subject:Date:From; b=gliAyOorbyz8o+HmTk1p2ycW1RUglrm0HFJ7jp1yCgmdNcyRLq7XBvVBEYpl8Lr4/ XbMvmLDX7zSFZsYYuYsMtdn4w3HIqiGetXwYXTwZKvg7NyEAWViWA7UDpwOsdcGDnZ FyiffEkZ/dpY4A3HPf5EQ9idZZT8gKQnB2v4WiozpEURUxwk2aXIwt3/cjvZd+/Z3q /hjfb4U78sDh2tPpMdB2BzAznmv8KoHyXWfl/VygoFp4cI1afxixDxoUjMswyTtWZB i06gIoKqISSKVeqvNuWyS9TWCwikulWwP3k/puiLBlL2TRNdSKkmrdxjSGhlBel+d3 v+i4UqCtifAAA== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Fri, 22 Jul 2016 20:20:11 +0900 Message-Id: <1469186411-5623-1-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 1.9.1 Subject: [U-Boot] [PATCH] ARM: uniphier: add clock/reset settings for xHCI of ProXstream2 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Deassert resets and enable clock signals of xHCI blocks if the corresponding CONFIG is enabled. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/clk/clk-pxs2.c | 7 ++++++- arch/arm/mach-uniphier/sc-regs.h | 4 ++++ 2 files changed, 10 insertions(+), 1 deletion(-) -- 1.9.1 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot diff --git a/arch/arm/mach-uniphier/clk/clk-pxs2.c b/arch/arm/mach-uniphier/clk/clk-pxs2.c index 76bf856..0d92405 100644 --- a/arch/arm/mach-uniphier/clk/clk-pxs2.c +++ b/arch/arm/mach-uniphier/clk/clk-pxs2.c @@ -4,6 +4,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include #include #include "../init.h" @@ -32,12 +33,16 @@ void uniphier_pxs2_clk_init(void) tmp |= SC_RSTCTRL2_NRST_USB3B1; writel(tmp, SC_RSTCTRL2); readl(SC_RSTCTRL2); /* dummy read */ + + tmp = readl(SC_RSTCTRL6); + tmp |= 0x37; + writel(tmp, SC_RSTCTRL6); #endif /* provide clocks */ tmp = readl(SC_CLKCTRL); #ifdef CONFIG_USB_XHCI_UNIPHIER - tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 | + tmp |= BIT(20) | BIT(19) | SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 | SC_CLKCTRL_CEN_GIO; #endif #ifdef CONFIG_UNIPHIER_ETH diff --git a/arch/arm/mach-uniphier/sc-regs.h b/arch/arm/mach-uniphier/sc-regs.h index a095589..98f1dea 100644 --- a/arch/arm/mach-uniphier/sc-regs.h +++ b/arch/arm/mach-uniphier/sc-regs.h @@ -68,6 +68,10 @@ #define SC_RSTCTRL4_NRST_UMC31 (0x1 << 5) /* UMC ch1 */ #define SC_RSTCTRL4_NRST_UMC30 (0x1 << 4) /* UMC ch0 */ +#define SC_RSTCTRL5 (SC_BASE_ADDR | 0x2010) + +#define SC_RSTCTRL6 (SC_BASE_ADDR | 0x2014) + #define SC_CLKCTRL (SC_BASE_ADDR | 0x2104) #define SC_CLKCTRL_CEN_USB31 (0x1 << 17) /* USB3 #1 */ #define SC_CLKCTRL_CEN_USB30 (0x1 << 16) /* USB3 #0 */