From patchwork Fri Jun 17 10:24:29 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 70302 Delivered-To: patch@linaro.org Received: by 10.140.28.4 with SMTP id 4csp203525qgy; Fri, 17 Jun 2016 03:23:34 -0700 (PDT) X-Received: by 10.194.41.170 with SMTP id g10mr1561636wjl.176.1466159013261; Fri, 17 Jun 2016 03:23:33 -0700 (PDT) Return-Path: Received: from theia.denx.de (theia.denx.de. [85.214.87.163]) by mx.google.com with ESMTP id jp7si11167428wjb.155.2016.06.17.03.23.33; Fri, 17 Jun 2016 03:23:33 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) client-ip=85.214.87.163; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A7CACA7641; Fri, 17 Jun 2016 12:23:32 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id itymZ0_tUO8q; Fri, 17 Jun 2016 12:23:32 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 465B3A755D; Fri, 17 Jun 2016 12:23:32 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6D078A7665 for ; Fri, 17 Jun 2016 12:23:29 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id TNDEFjp1FwNZ for ; Fri, 17 Jun 2016 12:23:29 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from conuserg-11.nifty.com (conuserg-11.nifty.com [210.131.2.78]) by theia.denx.de (Postfix) with ESMTPS id A7CC6A759C for ; Fri, 17 Jun 2016 12:23:24 +0200 (CEST) Received: from beagle.diag.org (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-11.nifty.com with ESMTP id u5HANA5d026719; Fri, 17 Jun 2016 19:23:12 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-11.nifty.com u5HANA5d026719 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1466158993; bh=sfBKQsJ/1N2Qarp5vhB6hTG4iuqv5Z5BixKbmxwFgto=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JGBHsolXILfwAy+u1YtM6RK30dvLtqmOf1dGpPE86ub/wpQH4121U/NJeFUyV7W9i mT4UdZhWd9M27Lvchz+q27GOwUaBdSTdN7j+FINfgb0znSgSjzoR2E+j9gQnm4kyXF 19GI2670C6fhUCSY+1wKx/ZbniStg8U21NXAlR5xP8zFZaF4nYsJx7ppD2GpZd5ttR Rxu/wy/YjQ7qoPn03E+dLH6P8/h+6FtPG2/qRsdp01RmBp+TilcaotrACwToQgE6Su cbjtg3uDWbU7015+eO8RpYTSjARYLgmpedPFjMUHWxlU3ik5oq6zmYngeQEVDaQN70 V3Hlbmy3Rz9gg== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Fri, 17 Jun 2016 19:24:29 +0900 Message-Id: <1466159070-9473-4-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1466159070-9473-1-git-send-email-yamada.masahiro@socionext.com> References: <1466159070-9473-1-git-send-email-yamada.masahiro@socionext.com> Subject: [U-Boot] [PATCH 3/4] ARM: uniphier: reserve memory for DRAM PHY training on PH1-LD20 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The DRAM PHY layer on PH1-LD20 is able to calibrate PHY parameters periodically. This compensates for the voltage and temperature deviation and improves the PHY parameter adjustment. Instead, it requires 64 byte scratch memory in each DRAM channel for the dynamic training. The memory regions must be reserved in DT before jumping to the kernel. The scratch area can be anywhere in each DRAM channel, but the DRAM init code in SPL currently assigns it at the end of each channel. So, it makes sense to reserve the regions on run-time by U-Boot instead of statically embedding it in the DT in Linux. Anyway, a boot-loader should know much more about memory initialization than the kernel. Signed-off-by: Masahiro Yamada --- arch/arm/Kconfig | 1 + arch/arm/mach-uniphier/Kconfig | 1 + arch/arm/mach-uniphier/dram_init.c | 40 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 42 insertions(+) -- 1.9.1 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e75c4c0..5aaae96 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -801,6 +801,7 @@ config ARCH_UNIPHIER select SPL select OF_CONTROL select SPL_OF_CONTROL + select OF_LIBFDT select DM select SPL_DM select DM_GPIO diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig index 89be0b3..e256eeb 100644 --- a/arch/arm/mach-uniphier/Kconfig +++ b/arch/arm/mach-uniphier/Kconfig @@ -40,6 +40,7 @@ config ARCH_UNIPHIER_LD11 config ARCH_UNIPHIER_LD20 bool "UniPhier PH1-LD20 SoC" select ARCH_UNIPHIER_64BIT + select OF_BOARD_SETUP endchoice diff --git a/arch/arm/mach-uniphier/dram_init.c b/arch/arm/mach-uniphier/dram_init.c index ef0e2e8..489366c 100644 --- a/arch/arm/mach-uniphier/dram_init.c +++ b/arch/arm/mach-uniphier/dram_init.c @@ -9,6 +9,9 @@ #include #include +#include "init.h" +#include "soc-info.h" + DECLARE_GLOBAL_DATA_PTR; static const void *get_memory_reg_prop(const void *fdt, int *lenp) @@ -81,3 +84,40 @@ void dram_init_banksize(void) (unsigned long)gd->bd->bi_dram[i].size); } } + +#ifdef CONFIG_OF_BOARD_SETUP +/* + * The DRAM PHY requires 64 byte scratch area in each DRAM channel + * for its dynamic PHY training feature. + */ +int ft_board_setup(void *fdt, bd_t *bd) +{ + const struct uniphier_board_data *param; + unsigned long rsv_addr; + const unsigned long rsv_size = 64; + int ch, ret; + + if (uniphier_get_soc_type() != SOC_UNIPHIER_LD20) + return 0; + + param = uniphier_get_board_param(); + if (!param) { + printf("failed to get board parameter\n"); + return -ENODEV; + } + + for (ch = 0; ch < param->dram_nr_ch; ch++) { + rsv_addr = param->dram_ch[ch].base + param->dram_ch[ch].size; + rsv_addr -= rsv_size; + + ret = fdt_add_mem_rsv(fdt, rsv_addr, rsv_size); + if (ret) + return -ENOSPC; + + printf(" Reserved memory region for DRAM PHY training: addr=%lx size=%lx\n", + rsv_addr, rsv_size); + } + + return 0; +} +#endif