From patchwork Wed Jun 8 09:02:32 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 69589 Delivered-To: patch@linaro.org Received: by 10.140.106.246 with SMTP id e109csp2381821qgf; Wed, 8 Jun 2016 02:01:35 -0700 (PDT) X-Received: by 10.28.29.143 with SMTP id d137mr6872044wmd.91.1465376495555; Wed, 08 Jun 2016 02:01:35 -0700 (PDT) Return-Path: Received: from theia.denx.de (theia.denx.de. [85.214.87.163]) by mx.google.com with ESMTP id zb7si288067wjb.123.2016.06.08.02.01.35; Wed, 08 Jun 2016 02:01:35 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) client-ip=85.214.87.163; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id F37EEA7517; Wed, 8 Jun 2016 11:01:34 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id YYRvIw6RRxNT; Wed, 8 Jun 2016 11:01:34 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 456A8A74EE; Wed, 8 Jun 2016 11:01:34 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D2995A7517 for ; Wed, 8 Jun 2016 11:01:24 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id mRjdbcUz9eOK for ; Wed, 8 Jun 2016 11:01:24 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from conuserg-10.nifty.com (conuserg-10.nifty.com [210.131.2.77]) by theia.denx.de (Postfix) with ESMTPS id 0521FA74EE for ; Wed, 8 Jun 2016 11:01:20 +0200 (CEST) Received: from beagle.diag.org (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-10.nifty.com with ESMTP id u5891Etw026546; Wed, 8 Jun 2016 18:01:15 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-10.nifty.com u5891Etw026546 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1465376475; bh=9ZCX4zF+zuBK78MII3Akt9Sqpe5FO1/OTt8SQ8uwlZo=; h=From:To:Cc:Subject:Date:From; b=ZokHSGHOBQFeDTKV6h0Um9XKbZ6z9MO82uOIcpyeaMxhsEo0+dxInvs3Vl7eZvfKk oK9rEqcqj3Jv8LPF5z7K0zg5tNSzQ7y/RW2GiHa35kTT7C4v9+DD/yM7Y+uJgWaP2t QGibbzmwcf5aa/d4aqVwtMeOMxbpxcS363oECZgNTdknd+bI0J5TBhnJrql/Seb8m1 NHgGLPLSYIjZ9pNDup5nqRCIyg1thFfopu2+pnMxeynMsm+fEGu43i2jYwrNzSYNK2 WDBeHAz1Jn7h6UCdtCpbOx4dbMe3ZX6CzYaUALnfIlrlOKzISR7sidaCsTIuV29Zwn mOCk18m0t4LiQ== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Wed, 8 Jun 2016 18:02:32 +0900 Message-Id: <1465376552-28129-1-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 1.9.1 Subject: [U-Boot] [PATCH v2] ARM: uniphier: insert dsb barrier to ensure visibility of store X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" I noticed secondary CPUs sometimes fail to wake up, and the root cause is that the sev instruction wakes up slave CPUs before the preceding the register write is observed by them. The read-back of the accessed register does not guarantee the order. In order to ensure the order between the register write and the sev instruction, a dsb instruction should be executed prior to the sev. Signed-off-by: Masahiro Yamada --- Changes in v2: - Use "dsb ishst" instead of "dsb sy" arch/arm/mach-uniphier/arm64/smp_kick_cpus.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 1.9.1 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot diff --git a/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c b/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c index 64412e0..5971ad2 100644 --- a/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c +++ b/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c @@ -21,11 +21,11 @@ void uniphier_smp_kick_all_cpus(void) rom_boot_rsv0 = map_sysmem(UNIPHIER_SMPCTRL_ROM_RSV0, SZ_8); writeq((u64)uniphier_secondary_startup, rom_boot_rsv0); - readq(rom_boot_rsv0); /* relax */ unmap_sysmem(rom_boot_rsv0); uniphier_smp_setup(); - asm("sev"); /* Bring up all secondary CPUs from Boot ROM into U-Boot */ + asm("dsb ishst\n" /* Ensure the write to ROM_RSV0 is visible */ + "sev"); /* Bring up all secondary CPUs from Boot ROM into U-Boot */ }