From patchwork Wed Apr 27 20:09:14 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Allred, Daniel" X-Patchwork-Id: 66837 Delivered-To: patch@linaro.org Received: by 10.140.93.198 with SMTP id d64csp2388303qge; Wed, 27 Apr 2016 13:11:57 -0700 (PDT) X-Received: by 10.194.185.179 with SMTP id fd19mr11289891wjc.107.1461787917154; Wed, 27 Apr 2016 13:11:57 -0700 (PDT) Return-Path: Received: from theia.denx.de (theia.denx.de. [85.214.87.163]) by mx.google.com with ESMTP id f14si9798134wmh.24.2016.04.27.13.11.56; Wed, 27 Apr 2016 13:11:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) client-ip=85.214.87.163; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 75BFAA77ED; Wed, 27 Apr 2016 22:11:15 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id YaBZaGnNaifZ; Wed, 27 Apr 2016 22:11:15 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9A1D8A77EE; Wed, 27 Apr 2016 22:10:25 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8C5ECA7705 for ; Wed, 27 Apr 2016 22:10:02 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id UsJEDrpDetSS for ; Wed, 27 Apr 2016 22:10:02 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from devils.ext.ti.com (devils.ext.ti.com [198.47.26.153]) by theia.denx.de (Postfix) with ESMTPS id 5DF5DA779F for ; Wed, 27 Apr 2016 22:09:56 +0200 (CEST) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id u3RK9s4K008810; Wed, 27 Apr 2016 15:09:54 -0500 Received: from DLEE70.ent.ti.com (dlee70.ent.ti.com [157.170.170.113]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id u3RK9sui027769; Wed, 27 Apr 2016 15:09:54 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.224.2; Wed, 27 Apr 2016 15:09:54 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id u3RK9s6d007994; Wed, 27 Apr 2016 15:09:54 -0500 Received: from localhost (houapbldadm.hou.asp.ti.com [10.219.18.42]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id u3RK9r925258; Wed, 27 Apr 2016 15:09:53 -0500 (CDT) From: Daniel Allred To: Date: Wed, 27 Apr 2016 15:09:14 -0500 Message-ID: <1461787759-31649-11-git-send-email-d-allred@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1461787759-31649-1-git-send-email-d-allred@ti.com> References: <1461787759-31649-1-git-send-email-d-allred@ti.com> MIME-Version: 1.0 Cc: Tom Rini , Madan Srinivas , Daniel Allred Subject: [U-Boot] [PATCH v2 10/15] ti_omap5_common: Update SPL start address on secure parts X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Updated the CONFIG_SPL_TEXT_BASE to support secure parts (moving the start address past secure reserved memory and the size of the security certificate that precedes the boot image on secure devices). Updated the related CONFIG_SPL_MAX_SIZE to properly reflect the internal memory actually available on the various device flavors (Common minimum internal RAM guaranteed for various flavors of DRA7xx/AM57xx is 512KB). Signed-off-by: Daniel Allred Signed-off-by: Madan Srinivas --- V2: Rename CONFIG_SECURE_BOOT_SRAM to TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ since it is not configurable (dependent on ROM/secure code). include/configs/ti_omap5_common.h | 32 +++++++++++++++++++++++++++----- 1 file changed, 27 insertions(+), 5 deletions(-) -- 1.9.1 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot Tested-by: Andreas Dannenberg diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index b049be4..d67860c 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -130,13 +130,35 @@ /* * SPL related defines. The Public RAM memory map the ROM defines the - * area between 0x40300000 and 0x4031E000 as a download area for OMAP5 - * (dra7xx is larger, but we do not need to be larger at this time). We - * set CONFIG_SPL_DISPLAY_PRINT to have omap_rev_string() called and + * area between 0x40300000 and 0x4031E000 as a download area for OMAP5. + * On DRA7xx/AM57XX the download area is between 0x40300000 and 0x4037E000. + * We set CONFIG_SPL_DISPLAY_PRINT to have omap_rev_string() called and * print some information. */ -#define CONFIG_SPL_TEXT_BASE 0x40300000 -#define CONFIG_SPL_MAX_SIZE (0x4031E000 - CONFIG_SPL_TEXT_BASE) +#ifdef CONFIG_TI_SECURE_DEVICE +/* + * For memory booting on HS parts, the first 4KB of the internal RAM is + * reserved for secure world use and the flash loader image is + * preceded by a secure certificate. The SPL will therefore run in internal + * RAM from address 0x40301350 (0x40300000+0x1000(reserved)+0x350(cert)). + */ +#define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ 0x1000 +#define CONFIG_SPL_TEXT_BASE 0x40301350 +#else +/* + * For all booting on GP parts, the flash loader image is + * downloaded into internal RAM at address 0x40300000. + */ +#define CONFIG_SPL_TEXT_BASE 0x40300000 +#endif + +/* DRA7xx/AM57xx have 512K of SRAM, OMAP5 only 128K */ +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) +#define CONFIG_SPL_BOOT_END 0x4037E000 +#else +#define CONFIG_SPL_BOOT_END 0x4031E000 +#endif +#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_BOOT_END - CONFIG_SPL_TEXT_BASE) #define CONFIG_SPL_DISPLAY_PRINT #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \