From patchwork Tue Apr 5 15:05:22 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Murphy X-Patchwork-Id: 65100 Delivered-To: patch@linaro.org Received: by 10.112.199.169 with SMTP id jl9csp521128lbc; Tue, 5 Apr 2016 08:07:59 -0700 (PDT) X-Received: by 10.194.111.229 with SMTP id il5mr18520788wjb.82.1459868879089; Tue, 05 Apr 2016 08:07:59 -0700 (PDT) Return-Path: Received: from theia.denx.de (theia.denx.de. [85.214.87.163]) by mx.google.com with ESMTP id c2si19791294wma.96.2016.04.05.08.07.58; Tue, 05 Apr 2016 08:07:59 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) client-ip=85.214.87.163; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 889454B77D; Tue, 5 Apr 2016 17:07:56 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id tZN-Bccv1VE4; Tue, 5 Apr 2016 17:07:56 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E5272A74A8; Tue, 5 Apr 2016 17:07:52 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 295DEA76A9 for ; Tue, 5 Apr 2016 17:05:54 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id iKwdlpg_qlGA for ; Tue, 5 Apr 2016 17:05:44 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from comal.ext.ti.com (comal.ext.ti.com [198.47.26.152]) by theia.denx.de (Postfix) with ESMTPS id 9373BA75BC for ; Tue, 5 Apr 2016 17:05:28 +0200 (CEST) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id u35F5OV6018558; Tue, 5 Apr 2016 10:05:24 -0500 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id u35F5O8C023242; Tue, 5 Apr 2016 10:05:24 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.224.2; Tue, 5 Apr 2016 10:05:23 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id u35F5OLW020237; Tue, 5 Apr 2016 10:05:24 -0500 Received: from localhost (a0272616local.am.dhcp.ti.com [172.22.189.209]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id u35F5N924575; Tue, 5 Apr 2016 10:05:24 -0500 (CDT) From: Dan Murphy To: Date: Tue, 5 Apr 2016 10:05:22 -0500 Message-ID: <1459868722-6371-2-git-send-email-dmurphy@ti.com> X-Mailer: git-send-email 2.7.2.333.g70bd996 In-Reply-To: <1459868722-6371-1-git-send-email-dmurphy@ti.com> References: <1459868722-6371-1-git-send-email-dmurphy@ti.com> MIME-Version: 1.0 Cc: edgar.iglesias@xilinx.com, trini@konsulko.com, michal.simek@xilinx.com Subject: [U-Boot] [uboot] [PATCH 2/2] net: phy: ti: Allow the driver to be more configurable X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Not all devices use the same internal delay or fifo depth. Add the ability to set the internal delay for rx or tx and the fifo depth via the devicetree. If the value is not set in the devicetree then set the delay to the default. If devicetree is not used then use the default defines within the driver. Signed-off-by: Dan Murphy --- RFC->v1 - Added devicetree support - https://patchwork.ozlabs.org/patch/604113/ drivers/net/phy/ti.c | 81 ++++++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 73 insertions(+), 8 deletions(-) -- 2.8.0.rc3 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c index c3912d5..e91a6ed 100644 --- a/drivers/net/phy/ti.c +++ b/drivers/net/phy/ti.c @@ -6,6 +6,14 @@ */ #include #include +#include +#include + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; /* TI DP83867 */ #define DP83867_DEVADDR 0x1f @@ -57,6 +65,17 @@ #define MII_MMD_CTRL_INCR_RDWT 0x8000 /* post increment on reads & writes */ #define MII_MMD_CTRL_INCR_ON_WT 0xC000 /* post increment on writes only */ +/* User setting - can be taken from DTS */ +#define DEFAULT_RX_ID_DELAY DP83867_RGMIIDCTL_2_25_NS +#define DEFAULT_TX_ID_DELAY DP83867_RGMIIDCTL_2_75_NS +#define DEFAULT_FIFO_DEPTH DP83867_PHYCR_FIFO_DEPTH_4_B_NIB + +struct dp83867_private { + int rx_id_delay; + int tx_id_delay; + int fifo_depth; +}; + /** * phy_read_mmd_indirect - reads data from the MMD registers * @phydev: The PHY device bus @@ -134,16 +153,58 @@ static inline bool phy_interface_is_rgmii(struct phy_device *phydev) phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID; } -/* User setting - can be taken from DTS */ -#define RX_ID_DELAY 8 -#define TX_ID_DELAY 0xa -#define FIFO_DEPTH 1 +#if defined(CONFIG_DM_ETH) +/** + * dp83867_data_init - Convenience function for setting PHY specific data + * + * @phydev: the phy_device struct + */ +static int dp83867_of_init(struct phy_device *phydev) +{ + struct dp83867_private *dp83867 = phydev->priv; + struct udevice *dev = phydev->dev; + + dp83867->rx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev->of_offset, + "ti,rx_int_delay", DEFAULT_RX_ID_DELAY); + + dp83867->tx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev->of_offset, + "ti,tx_int_delay", DEFAULT_TX_ID_DELAY); + + dp83867->fifo_depth = fdtdec_get_uint(gd->fdt_blob, dev->of_offset, + "ti,fifo_depth", DEFAULT_FIFO_DEPTH); + + return 0; +} +#else +static int dp83867_of_init(struct phy_device *phydev) +{ + dp83867->rx_id_delay = DEFAULT_RX_ID_DELAY; + dp83867->tx_id_delay = DEFAULT_TX_ID_DELAY; + dp83867->fifo_depth = DEFAULT_FIFO_DEPTH; + + return 0; +} +#endif static int dp83867_config(struct phy_device *phydev) { + struct dp83867_private *dp83867; unsigned int val, delay; int ret; + if (!phydev->priv) { + dp83867 = kzalloc(sizeof(*dp83867), GFP_KERNEL); + if (!dp83867) + return -ENOMEM; + + phydev->priv = dp83867; + ret = dp83867_of_init(phydev); + if (ret) + goto err_out; + } else { + dp83867 = (struct dp83867_private *)phydev->priv; + } + /* Restart the PHY. */ val = phy_read(phydev, MDIO_DEVAD_NONE, DP83867_CTRL); phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL, @@ -152,9 +213,9 @@ static int dp83867_config(struct phy_device *phydev) if (phy_interface_is_rgmii(phydev)) { ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL, (DP83867_MDI_CROSSOVER_AUTO << DP83867_MDI_CROSSOVER) | - (FIFO_DEPTH << DP83867_PHYCR_FIFO_DEPTH_SHIFT)); + (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT)); if (ret) - return ret; + goto err_out; } if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) && @@ -175,8 +236,8 @@ static int dp83867_config(struct phy_device *phydev) phy_write_mmd_indirect(phydev, DP83867_RGMIICTL, DP83867_DEVADDR, phydev->addr, val); - delay = (RX_ID_DELAY | - (TX_ID_DELAY << DP83867_RGMII_TX_CLK_DELAY_SHIFT)); + delay = (dp83867->rx_id_delay | + (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT)); phy_write_mmd_indirect(phydev, DP83867_RGMIIDCTL, DP83867_DEVADDR, phydev->addr, delay); @@ -184,6 +245,10 @@ static int dp83867_config(struct phy_device *phydev) genphy_config_aneg(phydev); return 0; + +err_out: + kfree(dp83867); + return ret; } static struct phy_driver DP83867_driver = {