From patchwork Wed Mar 23 15:14:18 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 64240 Delivered-To: patch@linaro.org Received: by 10.112.199.169 with SMTP id jl9csp90703lbc; Wed, 23 Mar 2016 08:14:48 -0700 (PDT) X-Received: by 10.28.73.66 with SMTP id w63mr4671682wma.53.1458746088259; Wed, 23 Mar 2016 08:14:48 -0700 (PDT) Return-Path: Received: from theia.denx.de (theia.denx.de. [85.214.87.163]) by mx.google.com with ESMTP id ki4si3746263wjb.8.2016.03.23.08.14.47; Wed, 23 Mar 2016 08:14:48 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) client-ip=85.214.87.163; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 986A3A74A8; Wed, 23 Mar 2016 16:14:45 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id S5Upcjexuodx; Wed, 23 Mar 2016 16:14:45 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6DC81A7514; Wed, 23 Mar 2016 16:14:44 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E49DBA74E9 for ; Wed, 23 Mar 2016 16:14:36 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Jm2xA0GH-aci for ; Wed, 23 Mar 2016 16:14:36 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from bear.ext.ti.com (bear.ext.ti.com [192.94.94.41]) by theia.denx.de (Postfix) with ESMTPS id 30551A74C3 for ; Wed, 23 Mar 2016 16:14:32 +0100 (CET) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id u2NFEUpJ029598; Wed, 23 Mar 2016 10:14:30 -0500 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id u2NFEUC2014440; Wed, 23 Mar 2016 10:14:30 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.224.2; Wed, 23 Mar 2016 10:14:29 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id u2NFEReJ001442; Wed, 23 Mar 2016 10:14:28 -0500 From: Nishanth Menon To: Tom Rini Date: Wed, 23 Mar 2016 10:14:18 -0500 Message-ID: <1458746059-17893-2-git-send-email-nm@ti.com> X-Mailer: git-send-email 2.8.0.rc3 In-Reply-To: <1458746059-17893-1-git-send-email-nm@ti.com> References: <1458746059-17893-1-git-send-email-nm@ti.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH 1/2] ARM: keystone2: Refactor MSMC macros to avoid #ifdeffery X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" MSMC segment Privilege ID is not consistent accross the keystone2 SoCs. As the first step to ensure complete SoC wide coherency setup, lets refactor the macros to remove the #if-deffery around the code which obfuscates which IDs are actually enabled for which SoC. As a result of this change the PCIe configuration is moved after the msmc configuration is complete, but that should ideally have no functional impact. Signed-off-by: Nishanth Menon --- arch/arm/mach-keystone/include/mach/hardware-k2e.h | 3 -- arch/arm/mach-keystone/include/mach/hardware-k2l.h | 3 -- arch/arm/mach-keystone/include/mach/hardware.h | 27 +++++++++----- arch/arm/mach-keystone/init.c | 43 ++++++++++++++++++---- 4 files changed, 53 insertions(+), 23 deletions(-) -- 2.8.0.rc3 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot diff --git a/arch/arm/mach-keystone/include/mach/hardware-k2e.h b/arch/arm/mach-keystone/include/mach/hardware-k2e.h index df499957e54d..e6bc77caaf09 100644 --- a/arch/arm/mach-keystone/include/mach/hardware-k2e.h +++ b/arch/arm/mach-keystone/include/mach/hardware-k2e.h @@ -34,9 +34,6 @@ #define KS2_LPSC_PCIE_1 27 #define KS2_LPSC_XGE 50 -/* MSMC */ -#define KS2_MSMC_SEGMENT_PCIE1 13 - /* Chip Interrupt Controller */ #define KS2_CIC2_DDR3_ECC_IRQ_NUM -1 /* not defined in K2E */ #define KS2_CIC2_DDR3_ECC_CHAN_NUM -1 /* not defined in K2E */ diff --git a/arch/arm/mach-keystone/include/mach/hardware-k2l.h b/arch/arm/mach-keystone/include/mach/hardware-k2l.h index a59e0713593f..92c17d7dd5ba 100644 --- a/arch/arm/mach-keystone/include/mach/hardware-k2l.h +++ b/arch/arm/mach-keystone/include/mach/hardware-k2l.h @@ -53,9 +53,6 @@ #define KS2_LPSC_FFTC_B 49 #define KS2_LPSC_IQN_AIL 50 -/* MSMC */ -#define KS2_MSMC_SEGMENT_PCIE1 14 - /* Chip Interrupt Controller */ #define KS2_CIC2_DDR3_ECC_IRQ_NUM 0x0D3 #define KS2_CIC2_DDR3_ECC_CHAN_NUM 0x01D diff --git a/arch/arm/mach-keystone/include/mach/hardware.h b/arch/arm/mach-keystone/include/mach/hardware.h index 8ca19bbcdbe9..dd9268fbf209 100644 --- a/arch/arm/mach-keystone/include/mach/hardware.h +++ b/arch/arm/mach-keystone/include/mach/hardware.h @@ -215,16 +215,23 @@ typedef volatile unsigned int *dv_reg_p; /* MSMC control */ #define KS2_MSMC_CTRL_BASE 0x0bc00000 #define KS2_MSMC_DATA_BASE 0x0c000000 -#ifndef CONFIG_SOC_K2G -#define KS2_MSMC_SEGMENT_TETRIS 8 -#define KS2_MSMC_SEGMENT_NETCP 9 -#define KS2_MSMC_SEGMENT_QM_PDSP 10 -#define KS2_MSMC_SEGMENT_PCIE0 11 -#else -#define KS2_MSMC_SEGMENT_TETRIS 1 -#define KS2_MSMC_SEGMENT_NETCP 4 -#define KS2_MSMC_SEGMENT_PCIE0 5 -#endif + +/* KS2 HK/L/E MSMC PRIVIDs for MSMC2 */ +#define K2HKLE_MSMC_SEGMENT_ARM 8 +#define K2HKLE_MSMC_SEGMENT_NETCP 9 +#define K2HKLE_MSMC_SEGMENT_QM_PDSP 10 +#define K2HKLE_MSMC_SEGMENT_PCIE0 11 + +/* K2L specific Privilege ID Settings */ +#define K2L_MSMC_SEGMENT_PCIE1 14 + +/* K2E specific Privilege ID Settings */ +#define K2E_MSMC_SEGMENT_PCIE1 13 + +/* K2G specific Privilege ID Settings */ +#define K2G_MSMC_SEGMENT_ARM 1 +#define K2G_MSMC_SEGMENT_NSS 4 +#define K2G_MSMC_SEGMENT_PCIE 5 /* MSMC segment size shift bits */ #define KS2_MSMC_SEG_SIZE_SHIFT 12 diff --git a/arch/arm/mach-keystone/init.c b/arch/arm/mach-keystone/init.c index aadd10bff270..2368315ff68c 100644 --- a/arch/arm/mach-keystone/init.c +++ b/arch/arm/mach-keystone/init.c @@ -96,22 +96,51 @@ static void config_pcie_mode(int pcie_port, enum pci_mode mode) __raw_writel(val, KS2_DEVCFG); } +static void msmc_k2hkle_common_setup(void) +{ + msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_ARM); + msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_NETCP); +#ifdef KS2_MSMC_SEGMENT_QM_PDSP + msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_QM_PDSP); +#endif + msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_PCIE0); +} + +static inline void msmc_k2l_setup(void) +{ + msmc_share_all_segments(K2L_MSMC_SEGMENT_PCIE1); +} + +static inline void msmc_k2e_setup(void) +{ + msmc_share_all_segments(K2E_MSMC_SEGMENT_PCIE1); +} + +static inline void msmc_k2g_setup(void) +{ + msmc_share_all_segments(K2G_MSMC_SEGMENT_ARM); + msmc_share_all_segments(K2G_MSMC_SEGMENT_NSS); + msmc_share_all_segments(K2G_MSMC_SEGMENT_PCIE); +} + int arch_cpu_init(void) { chip_configuration_unlock(); icache_enable(); - msmc_share_all_segments(KS2_MSMC_SEGMENT_TETRIS); - msmc_share_all_segments(KS2_MSMC_SEGMENT_NETCP); -#ifdef KS2_MSMC_SEGMENT_QM_PDSP - msmc_share_all_segments(KS2_MSMC_SEGMENT_QM_PDSP); -#endif - msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE0); + if (cpu_is_k2g()) { + msmc_k2g_setup(); + } else { + msmc_k2hkle_common_setup(); + if (cpu_is_k2e()) + msmc_k2e_setup(); + else if (cpu_is_k2l()) + msmc_k2l_setup(); + } /* Initialize the PCIe-0 to work as Root Complex */ config_pcie_mode(0, ROOTCOMPLEX); #if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L) - msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE1); /* Initialize the PCIe-1 to work as Root Complex */ config_pcie_mode(1, ROOTCOMPLEX); #endif