From patchwork Fri Mar 18 07:41:51 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 64031 Delivered-To: patch@linaro.org Received: by 10.112.199.169 with SMTP id jl9csp900416lbc; Fri, 18 Mar 2016 00:42:44 -0700 (PDT) X-Received: by 10.28.9.19 with SMTP id 19mr42239180wmj.87.1458286964513; Fri, 18 Mar 2016 00:42:44 -0700 (PDT) Return-Path: Received: from theia.denx.de (theia.denx.de. [85.214.87.163]) by mx.google.com with ESMTP id 199si15237317wmv.97.2016.03.18.00.42.44; Fri, 18 Mar 2016 00:42:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) client-ip=85.214.87.163; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 97C58A76F8; Fri, 18 Mar 2016 08:42:15 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id YJbGpbCTHq5H; Fri, 18 Mar 2016 08:42:15 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A978BA76DE; Fri, 18 Mar 2016 08:41:59 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0815BA7616 for ; Fri, 18 Mar 2016 08:41:27 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id mTVeZA-ElKS5 for ; Fri, 18 Mar 2016 08:41:26 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from conuserg012-v.nifty.com (conuserg012.nifty.com [202.248.44.38]) by theia.denx.de (Postfix) with ESMTPS id 7F8E0A76A9 for ; Fri, 18 Mar 2016 08:41:20 +0100 (CET) Received: from beagle.diag.org (p14090-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.90]) (authenticated) by conuserg012-v.nifty.com with ESMTP id u2I7f6Wg028808; Fri, 18 Mar 2016 16:41:14 +0900 X-Nifty-SrcIP: [153.142.97.90] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Fri, 18 Mar 2016 16:41:51 +0900 Message-Id: <1458286912-3475-13-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1458286912-3475-1-git-send-email-yamada.masahiro@socionext.com> References: <1458286912-3475-1-git-send-email-yamada.masahiro@socionext.com> Subject: [U-Boot] [PATCH 12/13] ARM: uniphier: add System Control register macros for ARMv8 SoCs X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The System Control block moved to a completely different register map for ARMv8 SoCs, so it cannot be shared with the ARM 32-bit ones. Define register macros in a new header file. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/sc64-regs.h | 44 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 arch/arm/mach-uniphier/sc64-regs.h -- 1.9.1 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot diff --git a/arch/arm/mach-uniphier/sc64-regs.h b/arch/arm/mach-uniphier/sc64-regs.h new file mode 100644 index 0000000..ef02830 --- /dev/null +++ b/arch/arm/mach-uniphier/sc64-regs.h @@ -0,0 +1,44 @@ +/* + * UniPhier SC (System Control) block registers for ARMv8 SoCs + * + * Copyright (C) 2016 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef SC64_REGS_H +#define SC64_REGS_H + +#define SC_BASE_ADDR 0x61840000 + +#define SC_RSTCTRL (SC_BASE_ADDR | 0x2000) +#define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008) +#define SC_RSTCTRL4 (SC_BASE_ADDR | 0x200c) +#define SC_RSTCTRL4_ETHER (1 << 6) +#define SC_RSTCTRL4_NAND (1 << 0) +#define SC_RSTCTRL5 (SC_BASE_ADDR | 0x2010) +#define SC_RSTCTRL6 (SC_BASE_ADDR | 0x2014) +#define SC_RSTCTRL7 (SC_BASE_ADDR | 0x2018) +#define SC_RSTCTRL7_UMCSB (1 << 16) +#define SC_RSTCTRL7_UMCA2 (1 << 10) +#define SC_RSTCTRL7_UMCA1 (1 << 9) +#define SC_RSTCTRL7_UMCA0 (1 << 8) +#define SC_RSTCTRL7_UMC32 (1 << 2) +#define SC_RSTCTRL7_UMC31 (1 << 1) +#define SC_RSTCTRL7_UMC30 (1 << 0) + +#define SC_CLKCTRL (SC_BASE_ADDR | 0x2100) +#define SC_CLKCTRL3 (SC_BASE_ADDR | 0x2108) +#define SC_CLKCTRL4 (SC_BASE_ADDR | 0x210c) +#define SC_CLKCTRL4_PERI (1 << 7) +#define SC_CLKCTRL4_ETHER (1 << 6) +#define SC_CLKCTRL4_NAND (1 << 0) +#define SC_CLKCTRL5 (SC_BASE_ADDR | 0x2110) +#define SC_CLKCTRL6 (SC_BASE_ADDR | 0x2114) +#define SC_CLKCTRL7 (SC_BASE_ADDR | 0x2118) +#define SC_CLKCTRL7_UMCSB (1 << 16) +#define SC_CLKCTRL7_UMC32 (1 << 2) +#define SC_CLKCTRL7_UMC31 (1 << 1) +#define SC_CLKCTRL7_UMC30 (1 << 0) + +#endif /* SC64_REGS_H */