From patchwork Tue Mar 15 15:25:52 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 63890 Delivered-To: patch@linaro.org Received: by 10.112.199.169 with SMTP id jl9csp734675lbc; Tue, 15 Mar 2016 08:27:27 -0700 (PDT) X-Received: by 10.194.76.161 with SMTP id l1mr30585555wjw.108.1458055647767; Tue, 15 Mar 2016 08:27:27 -0700 (PDT) Return-Path: Received: from theia.denx.de (theia.denx.de. [85.214.87.163]) by mx.google.com with ESMTP id ui6si33425068wjc.193.2016.03.15.08.27.27; Tue, 15 Mar 2016 08:27:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) client-ip=85.214.87.163; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id CE618A7703; Tue, 15 Mar 2016 16:27:15 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id nsq6f4AB8lxV; Tue, 15 Mar 2016 16:27:15 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D0062A7708; Tue, 15 Mar 2016 16:27:02 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3E6B4A76B0 for ; Tue, 15 Mar 2016 16:26:52 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ExWBnzeyXrbd for ; Tue, 15 Mar 2016 16:26:52 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from arroyo.ext.ti.com (arroyo.ext.ti.com [192.94.94.40]) by theia.denx.de (Postfix) with ESMTPS id AADAAA745C for ; Tue, 15 Mar 2016 16:26:47 +0100 (CET) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id u2FFQjo6029240; Tue, 15 Mar 2016 10:26:45 -0500 Received: from DLEE70.ent.ti.com (dlee70.ent.ti.com [157.170.170.113]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id u2FFQjFm029971; Tue, 15 Mar 2016 10:26:45 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.224.2; Tue, 15 Mar 2016 10:26:45 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id u2FFQidj028270; Tue, 15 Mar 2016 10:26:45 -0500 From: Nishanth Menon To: Tom Rini Date: Tue, 15 Mar 2016 10:25:52 -0500 Message-ID: <1458055553-10818-3-git-send-email-nm@ti.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1458055553-10818-1-git-send-email-nm@ti.com> References: <1458055553-10818-1-git-send-email-nm@ti.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH 2/3] ARM: keystone2: Convert BOOT_READ_BITFIELD into static inline function X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" BOOT_READ_BITFIELD can easily be a static inline function and be a little more readable with the same functionality. Reported-by: Tom Rini Signed-off-by: Nishanth Menon --- arch/arm/mach-keystone/include/mach/psc_defs.h | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) -- 2.7.0 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot diff --git a/arch/arm/mach-keystone/include/mach/psc_defs.h b/arch/arm/mach-keystone/include/mach/psc_defs.h index 9681175938d4..671b1d64d69f 100644 --- a/arch/arm/mach-keystone/include/mach/psc_defs.h +++ b/arch/arm/mach-keystone/include/mach/psc_defs.h @@ -34,7 +34,12 @@ static inline u32 _boot_bit_mask(u32 x, u32 y) return val << y; } -#define BOOT_READ_BITFIELD(z, x, y) ((((u32)z) & _boot_bit_mask(x, y)) >> (y)) +static inline u32 boot_read_bitfield(u32 z, u32 x, u32 y) +{ + u32 val = z & _boot_bit_mask(x, y); + return val >> y; +} + #define BOOT_SET_BITFIELD(z, f, x, y) ((((u32)z) & ~_boot_bit_mask(x, y)) | \ ((((u32)f) << (y)) & _boot_bit_mask(x, y))) @@ -43,25 +48,25 @@ static inline u32 _boot_bit_mask(u32 x, u32 y) #define PSC_REG_PDCTL_SET_PDMODE(x, y) BOOT_SET_BITFIELD((x), (y), 15, 12) /* PDSTAT */ -#define PSC_REG_PDSTAT_GET_STATE(x) BOOT_READ_BITFIELD((x), 4, 0) +#define PSC_REG_PDSTAT_GET_STATE(x) boot_read_bitfield((x), 4, 0) /* MDCFG */ -#define PSC_REG_MDCFG_GET_PD(x) BOOT_READ_BITFIELD((x), 20, 16) -#define PSC_REG_MDCFG_GET_RESET_ISO(x) BOOT_READ_BITFIELD((x), 14, 14) +#define PSC_REG_MDCFG_GET_PD(x) boot_read_bitfield((x), 20, 16) +#define PSC_REG_MDCFG_GET_RESET_ISO(x) boot_read_bitfield((x), 14, 14) /* MDCTL */ #define PSC_REG_MDCTL_SET_NEXT(x, y) BOOT_SET_BITFIELD((x), (y), 4, 0) #define PSC_REG_MDCTL_SET_LRSTZ(x, y) BOOT_SET_BITFIELD((x), (y), 8, 8) -#define PSC_REG_MDCTL_GET_LRSTZ(x) BOOT_READ_BITFIELD((x), 8, 8) +#define PSC_REG_MDCTL_GET_LRSTZ(x) boot_read_bitfield((x), 8, 8) #define PSC_REG_MDCTL_SET_RESET_ISO(x, y) BOOT_SET_BITFIELD((x), (y), \ 12, 12) /* MDSTAT */ -#define PSC_REG_MDSTAT_GET_STATUS(x) BOOT_READ_BITFIELD((x), 5, 0) -#define PSC_REG_MDSTAT_GET_LRSTZ(x) BOOT_READ_BITFIELD((x), 8, 8) -#define PSC_REG_MDSTAT_GET_LRSTDONE(x) BOOT_READ_BITFIELD((x), 9, 9) -#define PSC_REG_MDSTAT_GET_MRSTZ(x) BOOT_READ_BITFIELD((x), 10, 10) -#define PSC_REG_MDSTAT_GET_MRSTDONE(x) BOOT_READ_BITFIELD((x), 11, 11) +#define PSC_REG_MDSTAT_GET_STATUS(x) boot_read_bitfield((x), 5, 0) +#define PSC_REG_MDSTAT_GET_LRSTZ(x) boot_read_bitfield((x), 8, 8) +#define PSC_REG_MDSTAT_GET_LRSTDONE(x) boot_read_bitfield((x), 9, 9) +#define PSC_REG_MDSTAT_GET_MRSTZ(x) boot_read_bitfield((x), 10, 10) +#define PSC_REG_MDSTAT_GET_MRSTDONE(x) boot_read_bitfield((x), 11, 11) /* PDCTL states */ #define PSC_REG_VAL_PDCTL_NEXT_ON 1