From patchwork Fri Mar 4 06:56:16 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 63551 Delivered-To: patch@linaro.org Received: by 10.112.199.169 with SMTP id jl9csp302918lbc; Thu, 3 Mar 2016 22:56:14 -0800 (PST) X-Received: by 10.194.116.9 with SMTP id js9mr8510982wjb.112.1457074573189; Thu, 03 Mar 2016 22:56:13 -0800 (PST) Return-Path: Received: from theia.denx.de (theia.denx.de. [85.214.87.163]) by mx.google.com with ESMTP id x20si2396562wjq.196.2016.03.03.22.56.12; Thu, 03 Mar 2016 22:56:13 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) client-ip=85.214.87.163; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B9EA8A7671; Fri, 4 Mar 2016 07:56:10 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id FyaI1gfPNQPl; Fri, 4 Mar 2016 07:56:10 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 99C23A7678; Fri, 4 Mar 2016 07:56:06 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 50F60A745C for ; Fri, 4 Mar 2016 07:56:01 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id HsR-3y4ChniK for ; Fri, 4 Mar 2016 07:56:01 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from conuserg011-v.nifty.com (conuserg011.nifty.com [202.248.44.37]) by theia.denx.de (Postfix) with ESMTPS id 94382A7665 for ; Fri, 4 Mar 2016 07:55:56 +0100 (CET) Received: from beagle.diag.org (p14090-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.90]) (authenticated) by conuserg011-v.nifty.com with ESMTP id u246tVGX008940; Fri, 4 Mar 2016 15:55:32 +0900 X-Nifty-SrcIP: [153.142.97.90] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Fri, 4 Mar 2016 15:56:16 +0900 Message-Id: <1457074576-11757-1-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 1.9.1 Subject: [U-Boot] [PATCH] pinctrl: uniphier: set input-enable before pin-muxing X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" While IECTRL is disabled, input signals are pulled-down internally. If pin-muxing is set up first, glitch signals (Low to High transition) might be input to hardware blocks. Bad case scenario: [1] The hardware block is already running before pinctrl is handled. (the reset is de-asserted by default or by a firmware, for example) [2] The pin-muxing is set up. The input signals to hardware block are pulled-down by the chip-internal biasing. [3] The pins are input-enabled. The signals from the board reach the hardware block. Actually, one invalid character is input to the UART blocks for such SoCs as PH1-LD4, PH1-sLD8, where UART devices start to run at the power on reset. To avoid such problems, pins should be input-enabled before muxing. [ ported from Linux commit bac7f4c1bf5e7c6ccd5bb71edc015b26c77f7460 ] Fixes: 5dc626f83619 ("pinctrl: uniphier: add UniPhier pinctrl core support") Signed-off-by: Masahiro Yamada --- drivers/pinctrl/uniphier/pinctrl-uniphier-core.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -- 1.9.1 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c index 37a920c..ffdccab 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c @@ -74,6 +74,9 @@ static void uniphier_pinmux_set_one(struct udevice *dev, unsigned pin, unsigned reg, reg_end, shift, mask; u32 tmp; + /* some pins need input-enabling */ + uniphier_pinconf_input_enable(dev, pin); + reg = UNIPHIER_PINCTRL_PINMUX_BASE + pin * mux_bits / 32 * reg_stride; reg_end = reg + reg_stride; shift = pin * mux_bits % 32; @@ -94,9 +97,6 @@ static void uniphier_pinmux_set_one(struct udevice *dev, unsigned pin, if (priv->socdata->load_pinctrl) writel(1, priv->base + UNIPHIER_PINCTRL_LOAD_PINMUX); - - /* some pins need input-enabling */ - uniphier_pinconf_input_enable(dev, pin); } static int uniphier_pinmux_group_set(struct udevice *dev,