From patchwork Sun Feb 28 21:25:00 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sjoerd Simons X-Patchwork-Id: 63179 Delivered-To: patch@linaro.org Received: by 10.112.199.169 with SMTP id jl9csp1097739lbc; Mon, 29 Feb 2016 00:05:36 -0800 (PST) X-Received: by 10.194.115.196 with SMTP id jq4mr13289221wjb.101.1456733136088; Mon, 29 Feb 2016 00:05:36 -0800 (PST) Return-Path: Received: from theia.denx.de (theia.denx.de. [85.214.87.163]) by mx.google.com with ESMTP id e124si19047413wma.114.2016.02.29.00.05.35; Mon, 29 Feb 2016 00:05:36 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) client-ip=85.214.87.163; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 34E85A7655; Mon, 29 Feb 2016 09:05:31 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Lj6WXrE-f7_u; Mon, 29 Feb 2016 09:05:31 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id CBC8DA75FB; Mon, 29 Feb 2016 09:05:21 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 977FFA75DE for ; Mon, 29 Feb 2016 09:05:13 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id LAWLJRca84L6 for ; Mon, 29 Feb 2016 09:05:13 +0100 (CET) X-Greylist: delayed 553 seconds by postgrey-1.34 at theia; Mon, 29 Feb 2016 09:05:09 CET X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [46.235.227.227]) by theia.denx.de (Postfix) with ESMTPS id 35D91A7550 for ; Mon, 29 Feb 2016 09:05:09 +0100 (CET) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: sjoerd) with ESMTPSA id 967F2266467 Received: by dusk.luon.net (Postfix, from userid 1000) id 2AA3A228DD; Sun, 28 Feb 2016 22:25:06 +0100 (CET) From: Sjoerd Simons To: Simon Glass Date: Sun, 28 Feb 2016 22:25:00 +0100 Message-Id: <1456694706-911-7-git-send-email-sjoerd.simons@collabora.co.uk> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1456694706-911-1-git-send-email-sjoerd.simons@collabora.co.uk> References: <1456694706-911-1-git-send-email-sjoerd.simons@collabora.co.uk> Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v2 06/12] rockchip: rk3288: grf: Define GRF_SOC_CON1 and GRF_SOC_CON3 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add definitions for GRF_SOC_CON1 and GRF_SOC_CON3 which contain various GMAC related fields. Signed-off-by: Sjoerd Simons --- Changes in v2: None arch/arm/include/asm/arch-rockchip/grf_rk3288.h | 53 +++++++++++++++++++++++++ 1 file changed, 53 insertions(+) -- 2.7.0 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h index 0117a17..aaffd19 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h @@ -718,6 +718,40 @@ enum { MSCH0_MAINPARTIALPOP_MASK = 1, }; +/* GRF_SOC_CON1 */ +enum { + RMII_MODE_SHIFT = 0xe, + RMII_MODE_MASK = 1, + RMII_MODE = 1, + + GMAC_CLK_SEL_SHIFT = 0xc, + GMAC_CLK_SEL_MASK = 3, + GMAC_CLK_SEL_125M = 0, + GMAC_CLK_SEL_25M = 0x3, + GMAC_CLK_SEL_2_5M = 0x2, + + RMII_CLK_SEL_SHIFT = 0xb, + RMII_CLK_SEL_MASK = 1, + RMII_CLK_SEL_2_5M = 0, + RMII_CLK_SEL_25M, + + GMAC_SPEED_SHIFT = 0xa, + GMAC_SPEED_MASK = 1, + GMAC_SPEED_10M = 0, + GMAC_SPEED_100M, + + GMAC_FLOWCTRL_SHIFT = 0x9, + GMAC_FLOWCTRL_MASK = 1, + + GMAC_PHY_INTF_SEL_SHIFT = 0x6, + GMAC_PHY_INTF_SEL_MASK = 0x7, + GMAC_PHY_INTF_SEL_RGMII = 0x1, + GMAC_PHY_INTF_SEL_RMII = 0x4, + + HOST_REMAP_SHIFT = 0x5, + HOST_REMAP_MASK = 1 +}; + /* GRF_SOC_CON2 */ enum { UPCTL1_LPDDR3_ODT_EN_SHIFT = 0xd, @@ -765,4 +799,23 @@ enum { PWM_PWM = 0, }; +/* GRF_SOC_CON3 */ +enum { + RXCLK_DLY_ENA_GMAC_SHIFT = 0xf, + RXCLK_DLY_ENA_GMAC_MASK = 1, + RXCLK_DLY_ENA_GMAC_DISABLE = 0, + RXCLK_DLY_ENA_GMAC_ENABLE, + + TXCLK_DLY_ENA_GMAC_SHIFT = 0xe, + TXCLK_DLY_ENA_GMAC_MASK = 1, + TXCLK_DLY_ENA_GMAC_DISABLE = 0, + TXCLK_DLY_ENA_GMAC_ENABLE, + + CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, + CLK_RX_DL_CFG_GMAC_MASK = 0x7f, + + CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, + CLK_TX_DL_CFG_GMAC_MASK = 0x7f, +}; + #endif