From patchwork Fri Feb 26 05:21:45 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 62927 Delivered-To: patch@linaro.org Received: by 10.112.199.169 with SMTP id jl9csp528428lbc; Thu, 25 Feb 2016 21:22:06 -0800 (PST) X-Received: by 10.28.65.5 with SMTP id o5mr1056581wma.75.1456464126291; Thu, 25 Feb 2016 21:22:06 -0800 (PST) Return-Path: Received: from theia.denx.de (theia.denx.de. [85.214.87.163]) by mx.google.com with ESMTP id em4si13845301wjd.240.2016.02.25.21.22.06; Thu, 25 Feb 2016 21:22:06 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) client-ip=85.214.87.163; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8451FA77DB; Fri, 26 Feb 2016 06:21:58 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 3xjsyI0uVHm1; Fri, 26 Feb 2016 06:21:58 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3CEE0A77BB; Fri, 26 Feb 2016 06:21:53 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 464CAA7783 for ; Fri, 26 Feb 2016 06:21:28 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id mydDtv6mYxZI for ; Fri, 26 Feb 2016 06:21:28 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from conuserg009-v.nifty.com (conuserg009.nifty.com [202.248.44.35]) by theia.denx.de (Postfix) with ESMTPS id 2B6E9A773A for ; Fri, 26 Feb 2016 06:21:24 +0100 (CET) Received: from beagle.diag.org (p14090-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.90]) (authenticated) by conuserg009-v.nifty.com with ESMTP id u1Q5L8l8000668; Fri, 26 Feb 2016 14:21:16 +0900 X-Nifty-SrcIP: [153.142.97.90] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Fri, 26 Feb 2016 14:21:45 +0900 Message-Id: <1456464113-13901-14-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1456464113-13901-1-git-send-email-yamada.masahiro@socionext.com> References: <1456464113-13901-1-git-send-email-yamada.masahiro@socionext.com> Subject: [U-Boot] [PATCH 13/21] ARM: uniphier: support more DRAM use cases for PH1-sLD8 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Support DDR3-1600 / 512MB DDR size. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/dram/umc-ph1-sld8.c | 46 ++++++++++++++++++++++++++---- 1 file changed, 40 insertions(+), 6 deletions(-) -- 1.9.1 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c index 5e333e0..b8d729c 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c @@ -13,13 +13,29 @@ #include "ddrphy-regs.h" #include "umc-regs.h" +enum dram_freq { + DRAM_FREQ_1333M, + DRAM_FREQ_1600M, + DRAM_FREQ_NR, +}; + enum dram_size { DRAM_SZ_128M, DRAM_SZ_256M, + DRAM_SZ_512M, DRAM_SZ_NR, }; -static u32 umc_spcctla[DRAM_SZ_NR] = {0x00240512, 0x00350512}; +static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x55990b11, 0x66bb0f17}; +static u32 umc_cmdctla_plus[DRAM_FREQ_NR] = {0x45990b11, 0x46bb0f17}; +static u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x16958944, 0x18c6ab44}; +static u32 umc_cmdctlb_plus[DRAM_FREQ_NR] = {0x16958924, 0x18c6ab24}; +static u32 umc_spcctla[DRAM_FREQ_NR][DRAM_SZ_NR] = { + {0x00240512, 0x00350512, 0x00000000}, /* no data for 1333MHz,128MB */ + {0x002b0617, 0x003f0617, 0x00670617}, +}; +static u32 umc_spcctlb[DRAM_FREQ_NR] = {0x00ff0006, 0x00ff0008}; +static u32 umc_rdatactl[DRAM_FREQ_NR] = {0x000a00ac, 0x000c00ac}; static void umc_start_ssif(void __iomem *ssif_base) { @@ -58,8 +74,21 @@ static void umc_start_ssif(void __iomem *ssif_base) static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, int size, int freq, bool ddr3plus) { + enum dram_freq freq_e; enum dram_size size_e; + switch (freq) { + case 1333: + freq_e = DRAM_FREQ_1333M; + break; + case 1600: + freq_e = DRAM_FREQ_1600M; + break; + default: + pr_err("unsupported DRAM frequency %d MHz\n", freq); + return -EINVAL; + } + switch (size) { case 0: return 0; @@ -69,16 +98,21 @@ static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, case 2: size_e = DRAM_SZ_256M; break; + case 4: + size_e = DRAM_SZ_512M; + break; default: pr_err("unsupported DRAM size\n"); return -EINVAL; } - writel(ddr3plus ? 0x45990b11 : 0x55990b11, dramcont + UMC_CMDCTLA); - writel(ddr3plus ? 0x16958924 : 0x16958944, dramcont + UMC_CMDCTLB); - writel(umc_spcctla[size_e], dramcont + UMC_SPCCTLA); - writel(0x00ff0006, dramcont + UMC_SPCCTLB); - writel(0x000a00ac, dramcont + UMC_RDATACTL_D0); + writel((ddr3plus ? umc_cmdctla_plus : umc_cmdctla)[freq_e], + dramcont + UMC_CMDCTLA); + writel((ddr3plus ? umc_cmdctlb_plus : umc_cmdctlb)[freq_e], + dramcont + UMC_CMDCTLB); + writel(umc_spcctla[freq_e][size_e], dramcont + UMC_SPCCTLA); + writel(umc_spcctlb[freq_e], dramcont + UMC_SPCCTLB); + writel(umc_rdatactl[freq_e], dramcont + UMC_RDATACTL_D0); writel(0x04060806, dramcont + UMC_WDATACTL_D0); writel(0x04a02000, dramcont + UMC_DATASET); writel(0x00000000, ca_base + 0x2300);