From patchwork Thu Feb 25 18:53:44 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 62902 Delivered-To: patch@linaro.org Received: by 10.112.199.169 with SMTP id jl9csp319079lbc; Thu, 25 Feb 2016 10:54:44 -0800 (PST) X-Received: by 10.28.183.137 with SMTP id h131mr194795wmf.100.1456426484772; Thu, 25 Feb 2016 10:54:44 -0800 (PST) Return-Path: Received: from theia.denx.de (theia.denx.de. [85.214.87.163]) by mx.google.com with ESMTP id kk3si11346142wjc.43.2016.02.25.10.54.44; Thu, 25 Feb 2016 10:54:44 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) client-ip=85.214.87.163; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0DED9A7734; Thu, 25 Feb 2016 19:54:29 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id GvRoYxHMuvF8; Thu, 25 Feb 2016 19:54:28 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 52AE6A7765; Thu, 25 Feb 2016 19:54:12 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2A45CA74A6 for ; Thu, 25 Feb 2016 19:53:58 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id E356iE0pKzeV for ; Thu, 25 Feb 2016 19:53:58 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from bear.ext.ti.com (bear.ext.ti.com [192.94.94.41]) by theia.denx.de (Postfix) with ESMTPS id 244A6A7615 for ; Thu, 25 Feb 2016 19:53:52 +0100 (CET) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id u1PIrnN3027661; Thu, 25 Feb 2016 12:53:50 -0600 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id u1PIrnGC028590; Thu, 25 Feb 2016 12:53:49 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.224.2; Thu, 25 Feb 2016 12:53:49 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id u1PIrnDY031242; Thu, 25 Feb 2016 12:53:49 -0600 From: Nishanth Menon To: Tom Rini Date: Thu, 25 Feb 2016 12:53:44 -0600 Message-ID: <1456426427-23166-4-git-send-email-nm@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1456426427-23166-1-git-send-email-nm@ti.com> References: <1456426427-23166-1-git-send-email-nm@ti.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH V2 3/6] ARM: keystone2: psc: introduce function to hold and release module in reset. X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" These are useful for modules that need to be held in reset and are enabled for data to be loaded on to them. Typically these are microcontrollers or other processing entities in the system. Signed-off-by: Nishanth Menon --- V2: no change V1: https://patchwork.ozlabs.org/patch/510209/ arch/arm/mach-keystone/include/mach/psc_defs.h | 4 + arch/arm/mach-keystone/psc.c | 104 +++++++++++++++++++++++++ 2 files changed, 108 insertions(+) -- 2.7.0 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot diff --git a/arch/arm/mach-keystone/include/mach/psc_defs.h b/arch/arm/mach-keystone/include/mach/psc_defs.h index 2202946be5ea..6e6e7fd433a1 100644 --- a/arch/arm/mach-keystone/include/mach/psc_defs.h +++ b/arch/arm/mach-keystone/include/mach/psc_defs.h @@ -56,6 +56,8 @@ #define PSC_REG_MDSTAT_GET_STATUS(x) BOOT_READ_BITFIELD((x), 5, 0) #define PSC_REG_MDSTAT_GET_LRSTZ(x) BOOT_READ_BITFIELD((x), 8, 8) #define PSC_REG_MDSTAT_GET_LRSTDONE(x) BOOT_READ_BITFIELD((x), 9, 9) +#define PSC_REG_MDSTAT_GET_MRSTZ(x) BOOT_READ_BITFIELD((x), 10, 10) +#define PSC_REG_MDSTAT_GET_MRSTDONE(x) BOOT_READ_BITFIELD((x), 11, 11) /* PDCTL states */ #define PSC_REG_VAL_PDCTL_NEXT_ON 1 @@ -86,5 +88,7 @@ u32 psc_get_domain_num(u32 mod_num); int psc_enable_module(u32 mod_num); int psc_disable_module(u32 mod_num); int psc_disable_domain(u32 domain_num); +int psc_module_keep_in_reset_enabled(u32 mod_num, bool gate_clocks); +int psc_module_release_from_reset(u32 mod_num); #endif /* _PSC_DEFS_H_ */ diff --git a/arch/arm/mach-keystone/psc.c b/arch/arm/mach-keystone/psc.c index 8991e237735e..ff042a6db2dd 100644 --- a/arch/arm/mach-keystone/psc.c +++ b/arch/arm/mach-keystone/psc.c @@ -233,3 +233,107 @@ int psc_disable_domain(u32 domain_num) return psc_wait(domain_num); } + +/** + * psc_module_keep_in_reset_enabled() - Keep module in enabled,in-reset state + * @mod_num: LPSC module number + * @gate_clocks: Can the clocks be gated on this module? + * + * Enable the module, but do not release the module from local reset. This is + * necessary for many processor systems on keystone SoCs to allow for system + * initialization from a master processor prior to releasing the processor + * from reset. + */ +int psc_module_keep_in_reset_enabled(u32 mod_num, bool gate_clocks) +{ + u32 mdctl, ptcmd, mdstat; + u32 next_state; + int domain_num = psc_get_domain_num(mod_num); + int timeout = 100000; + + /* Wait for any previous transitions to complete */ + psc_wait(domain_num); + mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); + /* Should be set 0 to assert Local reset */ + if ((mdctl & PSC_REG_MDCTL_SET_LRSTZ(mdctl, 1))) { + mdctl = PSC_REG_MDCTL_SET_LRSTZ(mdctl, 0); + __raw_writel(mdctl, KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); + /* Wait for transition to take place */ + psc_wait(domain_num); + } + + /* Clear Module reset */ + mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); + next_state = gate_clocks ? PSC_REG_VAL_MDCTL_NEXT_OFF : + PSC_REG_VAL_MDCTL_NEXT_ON; + mdctl = PSC_REG_MDCTL_SET_NEXT(mdctl, next_state); + __raw_writel(mdctl, KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); + /* Trigger PD transition */ + ptcmd = __raw_readl(KS2_PSC_BASE + PSC_REG_PTCMD); + ptcmd |= (u32)(1 << domain_num); + __raw_writel(ptcmd, KS2_PSC_BASE + PSC_REG_PTCMD); + psc_wait(domain_num); + + mdstat = __raw_readl(KS2_PSC_BASE + PSC_REG_MDSTAT(mod_num)); + while (timeout) { + mdstat = __raw_readl(KS2_PSC_BASE + PSC_REG_MDSTAT(mod_num)); + + if (!(PSC_REG_MDSTAT_GET_STATUS(mdstat) & 0x30) && + PSC_REG_MDSTAT_GET_MRSTDONE(mdstat) && + PSC_REG_MDSTAT_GET_LRSTDONE(mdstat)) + break; + timeout--; + } + + if (!timeout) { + printf("%s: Timedout waiting for mdstat(0x%08x) to change\n", + __func__, mdstat); + return -ETIMEDOUT; + } + return 0; +} + +/** + * psc_module_release_from_reset() - Release the module from reset + * @mod_num: LPSC module number + * + * This is the follow through for the command 'psc_module_keep_in_reset_enabled' + * Allowing the module to be released from reset once all required inits are + * complete for the module. Typically, this allows the processor module to start + * execution. + */ +int psc_module_release_from_reset(u32 mod_num) +{ + u32 mdctl, mdstat; + int domain_num = psc_get_domain_num(mod_num); + int timeout = 100000; + + /* Wait for any previous transitions to complete */ + psc_wait(domain_num); + mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); + /* Should be set to 1 to de-assert Local reset */ + if ((mdctl & PSC_REG_MDCTL_SET_LRSTZ(mdctl, 0))) { + mdctl = PSC_REG_MDCTL_SET_LRSTZ(mdctl, 1); + __raw_writel(mdctl, KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); + /* Wait for transition to take place */ + psc_wait(domain_num); + } + mdstat = __raw_readl(KS2_PSC_BASE + PSC_REG_MDSTAT(mod_num)); + while (timeout) { + mdstat = __raw_readl(KS2_PSC_BASE + PSC_REG_MDSTAT(mod_num)); + + if (!(PSC_REG_MDSTAT_GET_STATUS(mdstat) & 0x30) && + PSC_REG_MDSTAT_GET_MRSTDONE(mdstat) && + PSC_REG_MDSTAT_GET_LRSTDONE(mdstat)) + break; + timeout--; + } + + if (!timeout) { + printf("%s: Timedout waiting for mdstat(0x%08x) to change\n", + __func__, mdstat); + return -ETIMEDOUT; + } + + return 0; +}