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[85.214.87.163]) by mx.google.com with ESMTP id ql9si20739578wjc.168.2015.05.11.01.04.12; Mon, 11 May 2015 01:04:12 -0700 (PDT) Received-SPF: none (google.com: u-boot-bounces@lists.denx.de does not designate permitted sender hosts) client-ip=85.214.87.163; Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id EEF8E4B622; Mon, 11 May 2015 10:04:11 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id OVHibmAZUz8k; Mon, 11 May 2015 10:04:11 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 306664B61C; Mon, 11 May 2015 10:04:11 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4CD5B4B61C for ; Mon, 11 May 2015 10:04:08 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id BJTCtpz3IzWf for ; Mon, 11 May 2015 10:04:08 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-la0-f45.google.com (mail-la0-f45.google.com [209.85.215.45]) by theia.denx.de (Postfix) with ESMTPS id 0C5614B61A for ; Mon, 11 May 2015 10:04:04 +0200 (CEST) Received: by laat2 with SMTP id t2so87661228laa.1 for ; Mon, 11 May 2015 01:04:03 -0700 (PDT) X-Received: by 10.152.28.73 with SMTP id z9mr7034054lag.93.1431331443757; Mon, 11 May 2015 01:04:03 -0700 (PDT) Received: from localhost.localdomain ([85.235.11.236]) by mx.google.com with ESMTPSA id do6sm2879721lac.19.2015.05.11.01.04.01 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 11 May 2015 01:04:02 -0700 (PDT) From: Linus Walleij To: u-boot@lists.denx.de, Albert Aribaud , Tom Rini , Simon Glass Date: Mon, 11 May 2015 10:03:57 +0200 Message-Id: <1431331437-27890-1-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 1.9.3 Cc: Steve Rae , u-boot-review@google.com Subject: [U-Boot] [PATCH] vexpress64: fix various memory issues X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: linus.walleij@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.50 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 The ARM Trusted Firmware or other security solutions are eating memory from the top of the physical SDRAM1 space, moving backward from 0xffffffff, currently occupying e.g. 0xfe000000-0xffffffff with Trusted Firmware. This solution to reserving memory for secure world is not optimal, so we need to think of how the secure world and earlier boot stages should communicate to U-Boot what memory they are eating up. For now let's just put 16MB aside. Also enable the memory test command and define start and end of the test range so we can check that we actually have all that memory available and working. Suggested-by: Axel Haslam Signed-off-by: Linus Walleij --- include/configs/vexpress_aemv8a.h | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h index 032010bb9e02..371e85b8f7be 100644 --- a/include/configs/vexpress_aemv8a.h +++ b/include/configs/vexpress_aemv8a.h @@ -113,9 +113,6 @@ #endif #endif /* !CONFIG_GICV3 */ -#define CONFIG_SYS_MEMTEST_START V2M_BASE -#define CONFIG_SYS_MEMTEST_END (V2M_BASE + 0x80000000) - /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_F_LEN 0x2000 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20)) @@ -182,8 +179,15 @@ /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2048 MB */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +/* Top 16MB reserved for secure world use */ +#define DRAM_SEC_SIZE 0x01000000 +#define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +/* Enable memtest */ +#define CONFIG_CMD_MEMTEST +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 +#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE) /* Initial environment variables */ #ifdef CONFIG_TARGET_VEXPRESS64_JUNO