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[85.214.87.163]) by mx.google.com with ESMTP id es6si2803346wib.105.2014.07.12.06.25.36 for ; Sat, 12 Jul 2014 06:25:37 -0700 (PDT) Received-SPF: none (google.com: u-boot-bounces@lists.denx.de does not designate permitted sender hosts) client-ip=85.214.87.163; Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 164CCA7C9E; Sat, 12 Jul 2014 15:25:19 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id QrFezXEh302F; Sat, 12 Jul 2014 15:25:18 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 71698AB673; Sat, 12 Jul 2014 15:24:41 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id ABB78AB648 for ; Sat, 12 Jul 2014 15:24:38 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id KgEyFdSOtnKC for ; Sat, 12 Jul 2014 15:24:37 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from benson.vm.bytemark.co.uk (benson.vm.bytemark.co.uk [212.110.190.137]) by theia.denx.de (Postfix) with ESMTPS id EBB6DAB64A for ; Sat, 12 Jul 2014 15:24:20 +0200 (CEST) Received: from cpc22-cmbg14-2-0-cust482.5-4.cable.virginm.net ([86.6.25.227] helo=celaeno.hellion.org.uk) by benson.vm.bytemark.co.uk with esmtpsa (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.72) (envelope-from ) id 1X5xHo-0005cC-47; Sat, 12 Jul 2014 14:24:20 +0100 Received: from dagon.hellion.org.uk ([192.168.1.7]) by celaeno.hellion.org.uk with smtp (Exim 4.80) (envelope-from ) id 1X5xHl-0000Le-MW; Sat, 12 Jul 2014 14:24:18 +0100 Received: by dagon.hellion.org.uk (sSMTP sendmail emulation); Sat, 12 Jul 2014 14:24:17 +0100 From: Ian Campbell To: u-boot@lists.denx.de, Albert Aribaud Date: Sat, 12 Jul 2014 14:24:05 +0100 Message-Id: <1405171448-27310-8-git-send-email-ijc@hellion.org.uk> X-Mailer: git-send-email 2.0.1 In-Reply-To: <1405171421.11981.51.camel@dagon.hellion.org.uk> References: <1405171421.11981.51.camel@dagon.hellion.org.uk> Cc: Tom Rini , Marc Zyngier Subject: [U-Boot] [PATCH v5 08/11] ARM: HYP/non-sec: add the option for a second-stage monitor X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: ijc@hellion.org.uk X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.172 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Marc Zyngier Allow the switch to a second stage secure monitor just before switching to non-secure. This allows a resident piece of firmware to be active once the kernel has been entered (the u-boot monitor is dead anyway, its pages being reused). Signed-off-by: Marc Zyngier Acked-by: Ian Campbell --- arch/arm/cpu/armv7/nonsec_virt.S | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index 2a43e3c..745670e 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -44,10 +44,19 @@ _monitor_vectors: * ip: target PC */ _secure_monitor: +#ifdef CONFIG_ARMV7_PSCI + ldr r5, =_psci_vectors @ Switch to the next monitor + mcr p15, 0, r5, c12, c0, 1 + isb + + @ Obtain a secure stack, and configure the PSCI backend + bl psci_arch_init +#endif + mrc p15, 0, r5, c1, c1, 0 @ read SCR - bic r5, r5, #0x4e @ clear IRQ, FIQ, EA, nET bits + bic r5, r5, #0x4a @ clear IRQ, EA, nET bits orr r5, r5, #0x31 @ enable NS, AW, FW bits - + @ FIQ preserved for secure mode mov r6, #SVC_MODE @ default mode is SVC is_cpu_virt_capable r4 #ifdef CONFIG_ARMV7_VIRT