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[85.214.87.163]) by mx.google.com with ESMTP id t4si2804473wif.107.2014.07.12.06.25.59 for ; Sat, 12 Jul 2014 06:26:00 -0700 (PDT) Received-SPF: none (google.com: u-boot-bounces@lists.denx.de does not designate permitted sender hosts) client-ip=85.214.87.163; Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6DAA8AB650; Sat, 12 Jul 2014 15:25:31 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id KpvSZuu9SYX4; Sat, 12 Jul 2014 15:25:31 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BFFA5AB682; Sat, 12 Jul 2014 15:24:50 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 96887AB64C for ; Sat, 12 Jul 2014 15:24:47 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id IeMbryDapmoc for ; Sat, 12 Jul 2014 15:24:47 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from benson.vm.bytemark.co.uk (benson.vm.bytemark.co.uk [212.110.190.137]) by theia.denx.de (Postfix) with ESMTPS id 3B301AB62F for ; Sat, 12 Jul 2014 15:24:24 +0200 (CEST) Received: from cpc22-cmbg14-2-0-cust482.5-4.cable.virginm.net ([86.6.25.227] helo=celaeno.hellion.org.uk) by benson.vm.bytemark.co.uk with esmtpsa (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.72) (envelope-from ) id 1X5xHr-0005ca-R2; Sat, 12 Jul 2014 14:24:23 +0100 Received: from dagon.hellion.org.uk ([192.168.1.7]) by celaeno.hellion.org.uk with smtp (Exim 4.80) (envelope-from ) id 1X5xHp-0000Lq-FK; Sat, 12 Jul 2014 14:24:22 +0100 Received: by dagon.hellion.org.uk (sSMTP sendmail emulation); Sat, 12 Jul 2014 14:24:21 +0100 From: Ian Campbell To: u-boot@lists.denx.de, Albert Aribaud Date: Sat, 12 Jul 2014 14:24:08 +0100 Message-Id: <1405171448-27310-11-git-send-email-ijc@hellion.org.uk> X-Mailer: git-send-email 2.0.1 In-Reply-To: <1405171421.11981.51.camel@dagon.hellion.org.uk> References: <1405171421.11981.51.camel@dagon.hellion.org.uk> Cc: Tom Rini , Marc Zyngier Subject: [U-Boot] [PATCH v5 11/11] ARM: HYP/non-sec: remove MIDR check to validate CBAR X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: ijc@hellion.org.uk X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.175 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Marc Zyngier Having a form of whitelist to check if we know of a CPU core and and obtain CBAR is a bit silly. It doesn't scale (how about A12, A17, as well as other I don't know about?), and is actually a property of the SoC, not the core. So either it works and everybody is happy, or it doesn't and the u-boot port to this SoC is providing the real address via a configuration option. The result of the above is that this code doesn't need to exist, is thus forcefully removed. Signed-off-by: Marc Zyngier Acked-by: Ian Campbell --- arch/arm/cpu/armv7/virt-v7.c | 17 ----------------- 1 file changed, 17 deletions(-) diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c index 6500030..651ca40 100644 --- a/arch/arm/cpu/armv7/virt-v7.c +++ b/arch/arm/cpu/armv7/virt-v7.c @@ -30,25 +30,8 @@ static unsigned long get_gicd_base_address(void) #ifdef CONFIG_ARM_GIC_BASE_ADDRESS return CONFIG_ARM_GIC_BASE_ADDRESS + GIC_DIST_OFFSET; #else - unsigned midr; unsigned periphbase; - /* check whether we are an Cortex-A15 or A7. - * The actual HYP switch should work with all CPUs supporting - * the virtualization extension, but we need the GIC address, - * which we know only for sure for those two CPUs. - */ - asm("mrc p15, 0, %0, c0, c0, 0\n" : "=r"(midr)); - switch (midr & MIDR_PRIMARY_PART_MASK) { - case MIDR_CORTEX_A9_R0P1: - case MIDR_CORTEX_A15_R0P0: - case MIDR_CORTEX_A7_R0P0: - break; - default: - printf("nonsec: could not determine GIC address.\n"); - return -1; - } - /* get the GIC base address from the CBAR register */ asm("mrc p15, 4, %0, c15, c0, 0\n" : "=r" (periphbase));