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[203.254.224.34]) by mx.google.com with ESMTP id sg3si14085014pbb.223.2013.10.29.00.22.13 for ; Tue, 29 Oct 2013 00:22:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.34 as permitted sender) client-ip=203.254.224.34; Received: from epcpsbgr5.samsung.com (u145.gpu120.samsung.co.kr [203.254.230.145]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MVF00E7S5RTKV80@mailout4.samsung.com>; Tue, 29 Oct 2013 16:22:12 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.122]) by epcpsbgr5.samsung.com (EPCPMTA) with SMTP id 7A.04.07052.4226F625; Tue, 29 Oct 2013 16:22:12 +0900 (KST) X-AuditID: cbfee691-b7f866d000001b8c-3c-526f622493fb Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 62.15.09687.4226F625; Tue, 29 Oct 2013 16:22:12 +0900 (KST) Received: from localhost.localdomain.com ([107.108.73.95]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MVF00H2J5SC3W70@mmp2.samsung.com>; Tue, 29 Oct 2013 16:22:12 +0900 (KST) From: Rajeshwari S Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, sjg@chromium.org, mk7.kang@samsung.com, chander.kashyap@linaro.org, u-boot-review@google.com, panto@antoniou-consulting.com, alim.akhtar@samsung.com, trini@ti.com Subject: [PATCH 10/10 V6] DWMMC: SMDK5420: Disable SMU for eMMC Date: Tue, 29 Oct 2013 12:53:13 +0530 Message-id: <1383031393-6093-11-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.11.7 In-reply-to: <1383031393-6093-1-git-send-email-rajeshwari.s@samsung.com> References: <1383031393-6093-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupmkeLIzCtJLcpLzFFi42JZI2JSpauSlB9k8Gm2icWDedvYLB6uv8li 0XGkhdFi1+3JLBZTDn9hsfi2ZRujxeTF85ktlr/eyG7xdm8nuwOnx7yfE5k8ZjdcZPFYsKnU 4861PWweZ+/sYPTo27KK0eP4je1MAexRXDYpqTmZZalF+nYJXBmtXU0sBb8lKyb2r2NuYFwu 2sXIySEhYCLx8vp+dghbTOLCvfVsXYxcHEICSxklflybww5T9Hz7PCaIxHRGicaZN1khnC4m iZuXr7J0MXJwsAFVbTyRANIgIiAh8av/KiNIDbPAPkaJ/d/XMIMkhAXsJTa8aQebyiKgKnGj 8SBYnFfAQ2Ll/r1Q2xQlZix5xghicwLF98z9A1YjJOAucXb7Y7ChEgL72CWOXmpmghgkIPFt 8iGwIyQEZCU2HWCGmCMpcXDFDZYJjMILGBlWMYqmFiQXFCelF5nqFSfmFpfmpesl5+duYgRG xOl/zybuYLx/wPoQYzLQuInMUqLJ+cCIyiuJNzQ2M7IwNTE1NjK3NCNNWEmcN/1RUpCQQHpi SWp2ampBalF8UWlOavEhRiYOTqkGRi794g3eVu+lS0+Y723fzxhod/q3xFmR7KSAXFWn3geX RA8sn/cx+9VW/2kCH+vMSj5POTh7bv3mC3xWiV3bp6+r+aHtLm16UjHmbPyrDbPqPuqV/vRL /iYStGx7RGTb/Uru+wqvVZXb7knaiW1onJR7JX6L0yn33bFHkwLK9d5eY7vHeSuVQYmlOCPR UIu5qDgRABTmwRaeAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrBIsWRmVeSWpSXmKPExsVy+t9jQV2VpPwgg9+fVSwezNvGZvFw/U0W i44jLYwWu25PZrGYcvgLi8W3LdsYLSYvns9ssfz1RnaLt3s72R04Peb9nMjkMbvhIovHgk2l Hneu7WHzOHtnB6NH35ZVjB7Hb2xnCmCPamC0yUhNTEktUkjNS85PycxLt1XyDo53jjc1MzDU NbS0MFdSyEvMTbVVcvEJ0HXLzAG6TUmhLDGnFCgUkFhcrKRvh2lCaIibrgVMY4Sub0gQXI+R ARpIWMOY0drVxFLwW7JiYv865gbG5aJdjJwcEgImEs+3z2OCsMUkLtxbz9bFyMUhJDCdUaJx 5k1WCKeLSeLm5assXYwcHGxAHRtPJIA0iAhISPzqv8oIUsMssI9RYv/3NcwgCWEBe4kNb9rZ QWwWAVWJG40HweK8Ah4SK/fvZYfYpigxY8kzRhCbEyi+Z+4fsBohAXeJs9sfM05g5F3AyLCK UTS1ILmgOCk911CvODG3uDQvXS85P3cTIzjenkntYFzZYHGIUYCDUYmH9wFzfpAQa2JZcWXu IUYJDmYlEd4dwUAh3pTEyqrUovz4otKc1OJDjMlAV01klhJNzgemgrySeENjE3NTY1NLEwsT M0vShJXEeQ+0WgcKCaQnlqRmp6YWpBbBbGHi4JRqYAw4//2Qukjqni0ZyjZSzT/3f/+8dNrs 2VMa9PqmnN2Q5Ojw5ODxpcLfZmxt/21tfiGlo813wuNXHyfviA1ku9ybbC6sGHFcua4o6rnb 7PNvlrZn7j1qeO6XkFXAoZJlqn7elw4+U1zHUSTM/V+rSXNn1azN/wycj0yRqj2vdWTlwWj9 XOZH4S+VWIozEg21mIuKEwH6hJ/0+wIAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: rajeshwari.s@samsung.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.212.45 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , SMDK5420 has a new Security Management Unit added for dwmmc driver, hence, configuring the control registers to support booting via eMMC. Signed-off-by: Alim Akhtar Signed-off-by: Rajeshwari Shinde Acked-by: Simon Glass Acked-by: Jaehoon Chung Acked-by: Pantelis Antoniou --- Changes in V3: - New patch. Changes in V4: Added flag to dissble SMU Changes in V5: - None Changes in V6: - Moved the SMU definitions to arch/arm dwmmc.h arch/arm/include/asm/arch-exynos/dwmmc.h | 13 +++++++++++++ drivers/mmc/dw_mmc.c | 11 +++++++++++ drivers/mmc/exynos_dw_mmc.c | 3 +++ include/dwmmc.h | 3 +++ 4 files changed, 30 insertions(+) diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h b/arch/arm/include/asm/arch-exynos/dwmmc.h index b9eca76..d1c5d4f 100644 --- a/arch/arm/include/asm/arch-exynos/dwmmc.h +++ b/arch/arm/include/asm/arch-exynos/dwmmc.h @@ -14,6 +14,19 @@ #define DWMCI_SET_DRV_CLK(x) ((x) << 16) #define DWMCI_SET_DIV_RATIO(x) ((x) << 24) +#define EMMCP_MPSBEGIN0 0x1200 +#define EMMCP_SEND0 0x1204 +#define EMMCP_CTRL0 0x120C + +#define MPSCTRL_SECURE_READ_BIT (0x1<<7) +#define MPSCTRL_SECURE_WRITE_BIT (0x1<<6) +#define MPSCTRL_NON_SECURE_READ_BIT (0x1<<5) +#define MPSCTRL_NON_SECURE_WRITE_BIT (0x1<<4) +#define MPSCTRL_USE_FUSE_KEY (0x1<<3) +#define MPSCTRL_ECB_MODE (0x1<<2) +#define MPSCTRL_ENCRYPTION (0x1<<1) +#define MPSCTRL_VALID (0x1<<0) + #ifdef CONFIG_OF_CONTROL int exynos_dwmmc_init(const void *blob); #endif diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index 9a803a0..a3506d4 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -11,6 +11,7 @@ #include #include #include +#include #define PAGE_SIZE 4096 @@ -301,6 +302,16 @@ static int dwmci_init(struct mmc *mmc) struct dwmci_host *host = (struct dwmci_host *)mmc->priv; u32 fifo_size; + if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) { + dwmci_writel(host, EMMCP_MPSBEGIN0, 0); + dwmci_writel(host, EMMCP_SEND0, 0); + dwmci_writel(host, EMMCP_CTRL0, + MPSCTRL_SECURE_READ_BIT | + MPSCTRL_SECURE_WRITE_BIT | + MPSCTRL_NON_SECURE_READ_BIT | + MPSCTRL_NON_SECURE_WRITE_BIT | MPSCTRL_VALID); + } + dwmci_writel(host, DWMCI_PWREN, 1); if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) { diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c index 4ef9fec..f7439a0 100644 --- a/drivers/mmc/exynos_dw_mmc.c +++ b/drivers/mmc/exynos_dw_mmc.c @@ -62,6 +62,9 @@ int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel) host->name = "EXYNOS DWMMC"; host->ioaddr = (void *)regbase; host->buswidth = bus_width; +#ifdef CONFIG_EXYNOS5420 + host->quirks = DWMCI_QUIRK_DISABLE_SMU; +#endif if (clksel) { host->clksel_val = clksel; diff --git a/include/dwmmc.h b/include/dwmmc.h index 08ced0b..6263140 100644 --- a/include/dwmmc.h +++ b/include/dwmmc.h @@ -123,6 +123,9 @@ #define DWMCI_BMOD_IDMAC_FB (1 << 1) #define DWMCI_BMOD_IDMAC_EN (1 << 7) +/* quirks */ +#define DWMCI_QUIRK_DISABLE_SMU (1 << 0) + struct dwmci_host { char *name; void *ioaddr;