From patchwork Fri Jun 7 10:56:21 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tushar Behera X-Patchwork-Id: 17669 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-ve0-f198.google.com (mail-ve0-f198.google.com [209.85.128.198]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 157F825E1F for ; Fri, 7 Jun 2013 11:10:45 +0000 (UTC) Received: by mail-ve0-f198.google.com with SMTP id jz10sf4193658veb.1 for ; Fri, 07 Jun 2013 04:10:44 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:x-beenthere:x-forwarded-to:x-forwarded-for :delivered-to:from:to:cc:subject:date:message-id:x-mailer :x-gm-message-state:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-google-group-id:list-post:list-help:list-archive:list-unsubscribe; bh=dzWh9JfT0jrJm7zWOuimQ/hY+oY+iQsFhTBM85n5QdM=; b=P+lAbfQSktPy2nB7SMIyTjM4gkNGUfwMm04+JOD9baoixJqxFafikXM1EgTqYLg/E1 QCmHa1cyOPw8wlnVwKDU1k+h+DO+lnik/7Kni1wn2uxb7wzKqBoC3iQ3nRxsQVFrLa2v 4XCKRyzmm0bgCp33VEhwMyxOvOweueggs6wHnzyR3eFpEPQrux8cbIGmuOiFQWvAeWX3 bMGVvmsxjGm+nGqGgDh9WskPcrE43QZ+1dPvyW6IQ9U4iIdeX/UgJSuzQVJjTbiN0jBr IkHbMjf/lZwkG+leREwy+HAoaNqlSRA2BhRGRlYadf6nsMw68O7k/EiguRW+qjsUPKEI OcRw== X-Received: by 10.236.14.233 with SMTP id d69mr22784115yhd.51.1370603444419; Fri, 07 Jun 2013 04:10:44 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.39.130 with SMTP id p2ls1742344qek.57.gmail; Fri, 07 Jun 2013 04:10:44 -0700 (PDT) X-Received: by 10.58.54.70 with SMTP id h6mr14169677vep.36.1370603444193; Fri, 07 Jun 2013 04:10:44 -0700 (PDT) Received: from mail-vc0-f180.google.com (mail-vc0-f180.google.com [209.85.220.180]) by mx.google.com with ESMTPS id sc6si43230659vdc.151.2013.06.07.04.10.44 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 07 Jun 2013 04:10:44 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.220.180 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.220.180; Received: by mail-vc0-f180.google.com with SMTP id gf11so651154vcb.39 for ; Fri, 07 Jun 2013 04:10:44 -0700 (PDT) X-Received: by 10.52.170.148 with SMTP id am20mr19994915vdc.75.1370603444105; Fri, 07 Jun 2013 04:10:44 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.221.10.206 with SMTP id pb14csp109603vcb; Fri, 7 Jun 2013 04:10:43 -0700 (PDT) X-Received: by 10.66.148.201 with SMTP id tu9mr2228799pab.56.1370603443171; Fri, 07 Jun 2013 04:10:43 -0700 (PDT) Received: from mail-pd0-f171.google.com (mail-pd0-f171.google.com [209.85.192.171]) by mx.google.com with ESMTPS id qs1si50825007pbc.346.2013.06.07.04.10.42 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 07 Jun 2013 04:10:43 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.192.171 is neither permitted nor denied by best guess record for domain of tushar.behera@linaro.org) client-ip=209.85.192.171; Received: by mail-pd0-f171.google.com with SMTP id y14so1785428pdi.16 for ; Fri, 07 Jun 2013 04:10:42 -0700 (PDT) X-Received: by 10.68.136.3 with SMTP id pw3mr37208405pbb.2.1370603442652; Fri, 07 Jun 2013 04:10:42 -0700 (PDT) Received: from linaro.sisodomain.com ([115.113.119.130]) by mx.google.com with ESMTPSA id vv6sm2701272pab.6.2013.06.07.04.10.39 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 07 Jun 2013 04:10:41 -0700 (PDT) From: Tushar Behera To: u-boot@lists.denx.de Cc: mk7.kang@samsung.com, k.chander@samsung.com, patches@linaro.org Subject: [PATCH] Origen: Set FIMD as the default display path Date: Fri, 7 Jun 2013 16:26:21 +0530 Message-Id: <1370602582-6332-1-git-send-email-tushar.behera@linaro.org> X-Mailer: git-send-email 1.7.9.5 X-Gm-Message-State: ALoCoQnjcvwHf8yd5vEmoRrGAPDzigr/aevR29n3zCmAmgAQY5H0qQTSPBR9LVt693NDT1mkns/2 X-Original-Sender: tushar.behera@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.180 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , On EXYNOS4210, there are three paths for display data to be processed, namely MIE, MDNIE and FIMD. On Origen board, FIMD display controller is used. Signed-off-by: Tushar Behera --- This patch is rebased on master branch of u-boot-samsung tree. board/samsung/origen/lowlevel_init.S | 13 +++++++++++++ board/samsung/origen/origen_setup.h | 7 +++++++ 2 files changed, 20 insertions(+) diff --git a/board/samsung/origen/lowlevel_init.S b/board/samsung/origen/lowlevel_init.S index be9d418..a7ea680 100644 --- a/board/samsung/origen/lowlevel_init.S +++ b/board/samsung/origen/lowlevel_init.S @@ -89,6 +89,7 @@ lowlevel_init: bl uart_asm_init bl arch_cpu_init bl tzpc_init + bl display_init pop {pc} wakeup_reset: @@ -96,6 +97,7 @@ wakeup_reset: bl mem_ctrl_asm_init bl arch_cpu_init bl tzpc_init + bl display_init exit_wakeup: /* Load return address and jump to kernel */ @@ -355,3 +357,14 @@ uart_asm_init: nop nop +/* Setting default display path to FIMD */ +display_init: + push {lr} + ldr r0, =EXYNOS4_SYSREG_BASE + + /* DISPLAY_CONTROL */ + ldr r1, =DISPLAY_CONTROL_VAL + ldr r2, =DISPLAY_CONTROL_OFFSET + str r1, [r0, r2] + + pop {pc} diff --git a/board/samsung/origen/origen_setup.h b/board/samsung/origen/origen_setup.h index 926a4cc..b0e1bc2 100644 --- a/board/samsung/origen/origen_setup.h +++ b/board/samsung/origen/origen_setup.h @@ -83,6 +83,8 @@ #define VPLL_CON0_OFFSET 0xC120 #define VPLL_CON1_OFFSET 0xC124 +#define DISPLAY_CONTROL_OFFSET 0x210 + /* DMC: DRAM Controllor Register offsets */ #define DMC_CONCONTROL 0x00 #define DMC_MEMCONTROL 0x04 @@ -485,6 +487,11 @@ | (VPLL_MRR << 24) \ | (VPLL_MFR << 16) \ | (VPLL_K << 0)) + +/* DISPLAY_CONTROL */ +#define FIMDBYPASS_LBLK0 0x1 +#define DISPLAY_CONTROL_VAL (FIMDBYPASS_LBLK0 << 1) + /* * UART GPIO_A0/GPIO_A1 Control Register Value * 0x2: UART Function