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[203.254.224.25]) by mx.google.com with ESMTP id ql7si1982465pbc.146.2013.04.26.23.09.20 for ; Fri, 26 Apr 2013 23:09:21 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of amarendra.xt@samsung.com designates 203.254.224.25 as permitted sender) client-ip=203.254.224.25; Received: from epcpsbgr5.samsung.com (u145.gpu120.samsung.co.kr [203.254.230.145]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MLW00H4XH30ZJA0@mailout2.samsung.com>; Sat, 27 Apr 2013 15:09:19 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.126]) by epcpsbgr5.samsung.com (EPCPMTA) with SMTP id 52.66.19350.F8B6B715; Sat, 27 Apr 2013 15:09:19 +0900 (KST) X-AuditID: cbfee691-b7fe56d000004b96-a2-517b6b8f9608 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 32.7D.01422.F8B6B715; Sat, 27 Apr 2013 15:09:19 +0900 (KST) Received: from amarendra-desktop.sisodomain.com ([107.108.73.18]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MLW00DPDH2TOT50@mmp2.samsung.com>; Sat, 27 Apr 2013 15:09:19 +0900 (KST) From: amar_g To: u-boot@lists.denx.de, jh80.chung@samsung.com Cc: patches@linaro.org, sjg@chromium.org, mk7.kang@samsung.com, chander.kashyap@linaro.org, afleming@gmail.com, hs@denx.de, Amar Subject: [PATCH V9 8/9] SMDK5250: Enable EMMC booting Date: Sat, 27 Apr 2013 11:42:59 +0530 Message-id: <1367043180-6756-9-git-send-email-amarendra.xt@samsung.com> X-Mailer: git-send-email 1.7.3.rc2 In-reply-to: <1367043180-6756-1-git-send-email-amarendra.xt@samsung.com> References: <1367043180-6756-1-git-send-email-amarendra.xt@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupgkeLIzCtJLcpLzFFi42JZI2JSp9ufXR1ocKNDw+LG9Z9sFl8WdLJb PFx/k8Vix537zBY3frWxWnQcaWG0mHL4C4vFty3bGC3e7u1kd+D0mN1wkcVj3qwTLB47Z91l 97hzbQ+bx9k7Oxg9+rasYgxgi+KySUnNySxLLdK3S+DKWHlqLUvBGcOKb9e2szYwvtboYuTk kBAwkdjaspUNwhaTuHBvPZDNxSEksJRR4nT7ERa4otYeFojEdEaJS43nWCGcCUwS5//NZQep YhNQl3jyaS0riC0iYCAx/cl2sCJmgfmMEou/PQIrEhYwlfj/6wAziM0ioCpx88ocJhCbV8Bd 4tKG31B3KEmc3/gabBCngIfEvxufweqFgGr2TZsKNlRCYBe7xKq5Z5ggBglIfJt8COg+DqCE rMQmiPkSApISB1fcYJnAKLyAkWEVo2hqQXJBcVJ6kalecWJucWleul5yfu4mRmAsnP73bOIO xvsHrA8xJgONm8gsJZqcD4ylvJJ4Q2MzIwtTE1NjI3NLM9KElcR51VusA4UE0hNLUrNTUwtS i+KLSnNSiw8xMnFwSjUwRvDq7J2m0ntwRs+/84zmMx7t6dW+0i6w8tW81SUaYbLsi8Jtv4l8 CNxfNFPzk9P5h28d4padu+09a8dRX+OTmyoCWqekrbXa5HFbk6tt7sOvWjL3GTYvrst8csRC Ir6cuYVzY73ePGOuGzxXvtbsLefs1r1YbCrAMTPq2GOX9EdzQ75s+K3zTImlOCPRUIu5qDgR AM3H7CmbAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrKIsWRmVeSWpSXmKPExsVy+t9jQd3+7OpAg/frZC1uXP/JZvFlQSe7 xcP1N1ksdty5z2xx41cbq0XHkRZGiymHv7BYfNuyjdHi7d5OdgdOj9kNF1k85s06weKxc9Zd do871/aweZy9s4PRo2/LKsYAtqgGRpuM1MSU1CKF1Lzk/JTMvHRbJe/geOd4UzMDQ11DSwtz JYW8xNxUWyUXnwBdt8wcoLuUFMoSc0qBQgGJxcVK+naYJoSGuOlawDRG6PqGBMH1GBmggYQ1 jBkrT61lKThjWPHt2nbWBsbXGl2MnBwSAiYSW1t7WCBsMYkL99azdTFycQgJTGeUuNR4jhXC mcAkcf7fXHaQKjYBdYknn9aygtgiAgYS059sBytiFpjPKLH42yOwImEBU4n/vw4wg9gsAqoS N6/MYQKxeQXcJS5t+M0GsU5J4vzG12CDOAU8JP7d+AxWLwRUs2/aVNYJjLwLGBlWMYqmFiQX FCel5xrpFSfmFpfmpesl5+duYgRH2jPpHYyrGiwOMQpwMCrx8GosqgoUYk0sK67MPcQowcGs JMKrmFodKMSbklhZlVqUH19UmpNafIgxGeiqicxSosn5wCSQVxJvaGxibmpsamliYWJmSZqw kjjvwVbrQCGB9MSS1OzU1ILUIpgtTBycUg2MrfeqI1YJ3dnke2czk83KiyfFl3pkn2V69kZ5 Ws7kIjWxoqhlHZrXXvyLvOJvUF1a2rk2l+VN8ITTwQaXgx5+vBf2yvrIywVzDx47xKPySmmJ 9gnTpieHp71etOLquikt6tdfNC9u2vT4uIFHSvcFqdX/7il0b+8rOBkwYS7LNrG7Arsbp15O qFBiKc5INNRiLipOBAD1KEq8+AIAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-Gm-Message-State: ALoCoQkDRbkFnsBMrVa6fXx7nuQWV/BqsK8GD08slfCwvRr2HNQt2eLLvQ1EL4qEzUR2yhBkQ9Tq X-Original-Sender: patch@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 2607:f8b0:400c:c02::230 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Amar This patch adds support for EMMC booting on SMDK5250. Signed-off-by: Amar --- Changes since V1: 1)Updated spl_boot.c file to maintain irom pointer table instead of using the #define values defined in header file. Changes since V2: 1)Updation of commit message and resubmition of proper patch set. Changes since V3: No change. Changes since V4: 1)The function get_irom_func(int index) has been added to avoid type casting at many places. 2)The changes to file arch/arm/include/asm/arch-exynos/clk.h are included in this patch file. Changes since V5: No change. Changes since V6: No change. Changes since V7: 1)The macros FSYS1_MMC0_DIV_MASK and FSYS1_MMC0_DIV_VAL are made local to file clock_init.c. Changes since V8: 1)Rebased. 2)Updated USB boot piece of code, to use get_irom_func(int index) to avoid type casting. --- board/samsung/smdk5250/clock_init.c | 18 ++++++++++ board/samsung/smdk5250/clock_init.h | 5 +++ board/samsung/smdk5250/spl_boot.c | 64 +++++++++++++++++++++++++++------- 3 files changed, 74 insertions(+), 13 deletions(-) diff --git a/board/samsung/smdk5250/clock_init.c b/board/samsung/smdk5250/clock_init.c index 5b9e82f..b288e66 100644 --- a/board/samsung/smdk5250/clock_init.c +++ b/board/samsung/smdk5250/clock_init.c @@ -28,10 +28,14 @@ #include #include #include +#include #include "clock_init.h" #include "setup.h" +#define FSYS1_MMC0_DIV_MASK 0xff0f +#define FSYS1_MMC0_DIV_VAL 0x0701 + DECLARE_GLOBAL_DATA_PTR; struct arm_clk_ratios arm_clk_ratios[] = { @@ -664,3 +668,17 @@ void clock_init_dp_clock(void) /* We run DP at 267 Mhz */ setbits_le32(&clk->div_disp1_0, CLK_DIV_DISP1_0_FIMD1); } + +/* + * Set clock divisor value for booting from EMMC. + * Set DWMMC channel-0 clk div to operate mmc0 device at 50MHz. + */ +void emmc_boot_clk_div_set(void) +{ + struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE; + unsigned int div_mmc; + + div_mmc = readl((unsigned int) &clk->div_fsys1) & ~FSYS1_MMC0_DIV_MASK; + div_mmc |= FSYS1_MMC0_DIV_VAL; + writel(div_mmc, (unsigned int) &clk->div_fsys1); +} diff --git a/board/samsung/smdk5250/clock_init.h b/board/samsung/smdk5250/clock_init.h index f751bcb..20a1d47 100644 --- a/board/samsung/smdk5250/clock_init.h +++ b/board/samsung/smdk5250/clock_init.h @@ -146,4 +146,9 @@ struct mem_timings *clock_get_mem_timings(void); * Initialize clock for the device */ void system_clock_init(void); + +/* + * Set clock divisor value for booting from EMMC. + */ +void emmc_boot_clk_div_set(void); #endif diff --git a/board/samsung/smdk5250/spl_boot.c b/board/samsung/smdk5250/spl_boot.c index c0bcf46..98f2286 100644 --- a/board/samsung/smdk5250/spl_boot.c +++ b/board/samsung/smdk5250/spl_boot.c @@ -23,16 +23,44 @@ #include #include +#include +#include +#include + +#include "clock_init.h" + +/* Index into irom ptr table */ +enum index { + MMC_INDEX, + EMMC44_INDEX, + EMMC44_END_INDEX, + SPI_INDEX, + USB_INDEX, +}; + +/* IROM Function Pointers Table */ +u32 irom_ptr_table[] = { + [MMC_INDEX] = 0x02020030, /* iROM Function Pointer-SDMMC boot */ + [EMMC44_INDEX] = 0x02020044, /* iROM Function Pointer-EMMC4.4 boot*/ + [EMMC44_END_INDEX] = 0x02020048,/* iROM Function Pointer + -EMMC4.4 end boot operation */ + [SPI_INDEX] = 0x02020058, /* iROM Function Pointer-SPI boot */ + [USB_INDEX] = 0x02020070, /* iROM Function Pointer-USB boot*/ + }; + enum boot_mode { BOOT_MODE_MMC = 4, BOOT_MODE_SERIAL = 20, + BOOT_MODE_EMMC = 8, /* EMMC4.4 */ /* Boot based on Operating Mode pin settings */ BOOT_MODE_OM = 32, BOOT_MODE_USB, /* Boot using USB download */ }; - typedef u32 (*spi_copy_func_t)(u32 offset, u32 nblock, u32 dst); - typedef u32 (*usb_copy_func_t)(void); +void *get_irom_func(int index) +{ + return (void *)*(u32 *)irom_ptr_table[index]; +} /* * Set/clear program flow prediction and return the previous state. @@ -55,13 +83,15 @@ static int config_branch_prediction(int set_cr_z) */ void copy_uboot_to_ram(void) { - spi_copy_func_t spi_copy; - usb_copy_func_t usb_copy; - int is_cr_z_set; unsigned int sec_boot_check; enum boot_mode bootmode = BOOT_MODE_OM; - u32 (*copy_bl2)(u32, u32, u32); + + u32 (*spi_copy)(u32 offset, u32 nblock, u32 dst); + u32 (*copy_bl2)(u32 offset, u32 nblock, u32 dst); + u32 (*copy_bl2_from_emmc)(u32 nblock, u32 dst); + void (*end_bootop_from_emmc)(void); + u32 (*usb_copy)(void); /* Read iRAM location to check for secondary USB boot mode */ sec_boot_check = readl(EXYNOS_IRAM_SECONDARY_BASE); @@ -73,14 +103,24 @@ void copy_uboot_to_ram(void) switch (bootmode) { case BOOT_MODE_SERIAL: - spi_copy = *(spi_copy_func_t *)EXYNOS_COPY_SPI_FNPTR_ADDR; + spi_copy = get_irom_func(SPI_INDEX); spi_copy(SPI_FLASH_UBOOT_POS, CONFIG_BL2_SIZE, - CONFIG_SYS_TEXT_BASE); + CONFIG_SYS_TEXT_BASE); break; case BOOT_MODE_MMC: - copy_bl2 = (void *) *(u32 *)COPY_BL2_FNPTR_ADDR; + copy_bl2 = get_irom_func(MMC_INDEX); copy_bl2(BL2_START_OFFSET, BL2_SIZE_BLOC_COUNT, - CONFIG_SYS_TEXT_BASE); + CONFIG_SYS_TEXT_BASE); + break; + case BOOT_MODE_EMMC: + /* Set the FSYS1 clock divisor value for EMMC boot */ + emmc_boot_clk_div_set(); + + copy_bl2_from_emmc = get_irom_func(EMMC44_INDEX); + end_bootop_from_emmc = get_irom_func(EMMC44_END_INDEX); + + copy_bl2_from_emmc(BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE); + end_bootop_from_emmc(); break; case BOOT_MODE_USB: /* @@ -88,8 +128,7 @@ void copy_uboot_to_ram(void) * before copy from USB device to RAM */ is_cr_z_set = config_branch_prediction(0); - usb_copy = *(usb_copy_func_t *) - EXYNOS_COPY_USB_FNPTR_ADDR; + usb_copy = get_irom_func(USB_INDEX); usb_copy(); config_branch_prediction(is_cr_z_set); break; @@ -117,5 +156,4 @@ void board_init_r(gd_t *id, ulong dest_addr) while (1) ; } - void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) {}