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[203.254.224.25]) by mx.google.com with ESMTP id ye6si5244167pbc.210.2013.04.26.23.09.11 for ; Fri, 26 Apr 2013 23:09:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of amarendra.xt@samsung.com designates 203.254.224.25 as permitted sender) client-ip=203.254.224.25; Received: from epcpsbgr5.samsung.com (u145.gpu120.samsung.co.kr [203.254.230.145]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MLW00H4XH30ZJA0@mailout2.samsung.com>; Sat, 27 Apr 2013 15:09:11 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.126]) by epcpsbgr5.samsung.com (EPCPMTA) with SMTP id 89.56.19350.68B6B715; Sat, 27 Apr 2013 15:09:10 +0900 (KST) X-AuditID: cbfee691-b7fe56d000004b96-6a-517b6b869544 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 8C.6D.01422.68B6B715; Sat, 27 Apr 2013 15:09:10 +0900 (KST) Received: from amarendra-desktop.sisodomain.com ([107.108.73.18]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MLW00DPDH2TOT50@mmp2.samsung.com>; Sat, 27 Apr 2013 15:09:10 +0900 (KST) From: amar_g To: u-boot@lists.denx.de, jh80.chung@samsung.com Cc: patches@linaro.org, sjg@chromium.org, mk7.kang@samsung.com, chander.kashyap@linaro.org, afleming@gmail.com, hs@denx.de, Amar Subject: [PATCH V9 3/9] DWMMC: Initialise dwmci and resolve EMMC read write issues Date: Sat, 27 Apr 2013 11:42:54 +0530 Message-id: <1367043180-6756-4-git-send-email-amarendra.xt@samsung.com> X-Mailer: git-send-email 1.7.3.rc2 In-reply-to: <1367043180-6756-1-git-send-email-amarendra.xt@samsung.com> References: <1367043180-6756-1-git-send-email-amarendra.xt@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpnkeLIzCtJLcpLzFFi42JZI2JSp9uWXR1osGKjtcWN6z/ZLL4s6GS3 eLj+JovFjjv3mS1u/Gpjteg40sJoMeXwFxaLb1u2MVq83dvJ7sDpMbvhIovHvFknWDx2zrrL 7nHn2h42j7N3djB69G1ZxRjAFsVlk5Kak1mWWqRvl8CV0XjpNVvBQsmKeb3NTA2M00W6GDk5 JARMJP61vmOEsMUkLtxbz9bFyMUhJLCUUaLt4UymLkYOsKLuPz4Q8emMEn1tj9khnAlMEhen vGYF6WYTUJd48mktmC0iYCAx/cl2VpAiZoH5jBKLvz1iB0kIC4RIfDrxmAXEZhFQlWha+R+s gVfAXWJR52lWiDOUJM5vhBjKKeAh8e/GZ2YQWwioZt+0qWBDJQS2sUvMezGZFWKQgMS3yYdY IE6Vldh0gBlijqTEwRU3WCYwCi9gZFjFKJpakFxQnJReZKpXnJhbXJqXrpecn7uJERgJp/89 m7iD8f4B60OMyUDjJjJLiSbnAyMpryTe0NjMyMLUxNTYyNzSjDRhJXFe9RbrQCGB9MSS1OzU 1ILUovii0pzU4kOMTBycUg2MFZozp7gYBRrWpR83fLXm6f4Dc833sO9Nk5wnmDVFdzqruu0N IXMr+/SSlLbmR2mvdu4uyDd4I2f+/5ORt3qItKnxBN+waf9PPJk+rbttca5U1kV3+/2f6gX5 zRIm/NluVP/twXHhuE1VOp3Zx73/zyvwsY1vf+LSvYTtasA1IX2ptaGHXM8psRRnJBpqMRcV JwIALt59lZoCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrCIsWRmVeSWpSXmKPExsVy+t9jQd227OpAg8vHDC1uXP/JZvFlQSe7 xcP1N1ksdty5z2xx41cbq0XHkRZGiymHv7BYfNuyjdHi7d5OdgdOj9kNF1k85s06weKxc9Zd do871/aweZy9s4PRo2/LKsYAtqgGRpuM1MSU1CKF1Lzk/JTMvHRbJe/geOd4UzMDQ11DSwtz JYW8xNxUWyUXnwBdt8wcoLuUFMoSc0qBQgGJxcVK+naYJoSGuOlawDRG6PqGBMH1GBmggYQ1 jBmNl16zFSyUrJjX28zUwDhdpIuRg0NCwESi+49PFyMnkCkmceHeerYuRi4OIYHpjBJ9bY/Z IZwJTBIXp7xmBaliE1CXePJpLZgtImAgMf3JdlaQImaB+YwSi789YgdJCAuESHw68ZgFxGYR UJVoWvkfrIFXwF1iUedpVoh1ShLnN0IM5RTwkPh34zMziC0EVLNv2lTWCYy8CxgZVjGKphYk FxQnpeca6RUn5haX5qXrJefnbmIEx9kz6R2MqxosDjEKcDAq8fBqLKoKFGJNLCuuzD3EKMHB rCTCq5haHSjEm5JYWZValB9fVJqTWnyIMRnoqonMUqLJ+cAUkFcSb2hsYm5qbGppYmFiZkma sJI478FW60AhgfTEktTs1NSC1CKYLUwcnFINjD2sK+36rhjdc2jicd8dUPPgn8fOyxpSX9jK 9NM1el0m9SQE6T1cNTfH1EvTmcV09nPx9cUlb7Z7be6PWzBJn/0rR2SKpPUbHZlrrC+/mM+w DE5jri+4nFy6/u8ZcSUG/QtGXaIsllZzvcQbt1wwvPGqTSDMfOqaE77qCh8bW85EvDLWdw1Q YinOSDTUYi4qTgQAVc4zO/cCAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-Gm-Message-State: ALoCoQnkMa8q15tLHjgnuMtlbH/6Ch6TU4776lvGyrVGBurueYCztrD2+xco0KuvueVMDK5FVzhm X-Original-Sender: patch@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 2607:f8b0:400c:c02::22a is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Amar This patch enumerates dwmci and set auto stop command during dwmci initialisation. EMMC read/write is not happening in current implementation due to improper fifo size computation. Hence modified the fifo size computation to resolve EMMC read write issues. Signed-off-by: Amar Acked-by: Jaehoon Chung --- Changes since V1: 1)Created the macros RX_WMARK_SHIFT and RX_WMARK_MASK in header file. Changes since V2: 1)Updation of commit message and resubmition of proper patch set. Changes since V3: 1)Updated to use the macro DWMCI_CTRL_SEND_AS_CCSD instead of the hard coded value (1 << 10). Changes since V4: 1)Updated the function dwmci_send_cmd() to use get_timer() instead of using mdelay(1). Changes since V5: 1)Updated in response to review comments. Changes since V6: No change. Changes since V7: 1)Updated the function dwmci_setup_bus() to return 0 if (freq == 0). This is to avoid the run time exception "raise:Signal # 8 caught". Changes since V8: 1)Auto stop command is disabled, as this feature is not required. --- drivers/mmc/dw_mmc.c | 21 ++++++++++++--------- 1 files changed, 12 insertions(+), 9 deletions(-) diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index 4070d4e..1307b12 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -129,13 +129,13 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, unsigned int timeout = 100000; u32 retry = 10000; u32 mask, ctrl; + ulong start = get_timer(0); while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) { - if (timeout == 0) { + if (get_timer(start) > timeout) { printf("Timeout on data busy\n"); return TIMEOUT; } - timeout--; } dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL); @@ -143,7 +143,6 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, if (data) dwmci_prepare_data(host, data); - dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg); if (data) @@ -231,9 +230,8 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) int timeout = 10000; unsigned long sclk; - if (freq == host->clock) + if ((freq == host->clock) || (freq == 0)) return 0; - /* * If host->mmc_clk didn't define, * then assume that host->bus_hz is source clock value. @@ -323,6 +321,9 @@ static int dwmci_init(struct mmc *mmc) return -1; } + /* Enumerate at 400KHz */ + dwmci_setup_bus(host, mmc->f_min); + dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF); dwmci_writel(host, DWMCI_INTMASK, 0); @@ -332,11 +333,13 @@ static int dwmci_init(struct mmc *mmc) dwmci_writel(host, DWMCI_BMOD, 1); fifo_size = dwmci_readl(host, DWMCI_FIFOTH); - if (host->fifoth_val) + fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1; + if (host->fifoth_val) { fifoth_val = host->fifoth_val; - else - fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size/2 -1) | - TX_WMARK(fifo_size/2); + } else { + fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) | + TX_WMARK(fifo_size / 2); + } dwmci_writel(host, DWMCI_FIFOTH, fifoth_val); dwmci_writel(host, DWMCI_CLKENA, 0);