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[203.254.224.24]) by mx.google.com with ESMTP id oy4si6827727pac.244.2013.04.03.06.53.56; Wed, 03 Apr 2013 06:53:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of amarendra.xt@samsung.com designates 203.254.224.24 as permitted sender) client-ip=203.254.224.24; Received: from epcpsbgr4.samsung.com (u144.gpu120.samsung.co.kr [203.254.230.144]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MKO00AOJMLO7P90@mailout1.samsung.com>; Wed, 03 Apr 2013 22:53:48 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.125]) by epcpsbgr4.samsung.com (EPCPMTA) with SMTP id E2.2B.02019.C643C515; Wed, 03 Apr 2013 22:53:48 +0900 (KST) X-AuditID: cbfee690-b7f656d0000007e3-7f-515c346cda71 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id C2.2F.17838.C643C515; Wed, 03 Apr 2013 22:53:48 +0900 (KST) Received: from chrome-ubuntu.sisodomain.com ([107.108.73.106]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MKO00KW6MDEHT20@mmp2.samsung.com>; Wed, 03 Apr 2013 22:53:48 +0900 (KST) From: Amar To: u-boot@lists.denx.de, mk7.kang@samsung.com Cc: patches@linaro.org, sjg@chromium.org, chander.kashyap@linaro.org, afleming@gmail.com, jh80.chung@samsung.com, u-boot-review@google.com Subject: [PATCH V8 8/9] SMDK5250: Enable EMMC booting Date: Wed, 03 Apr 2013 10:08:32 -0400 Message-id: <1364998113-13428-9-git-send-email-amarendra.xt@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1364998113-13428-1-git-send-email-amarendra.xt@samsung.com> References: <1364998113-13428-1-git-send-email-amarendra.xt@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpgkeLIzCtJLcpLzFFi42JZI2JSq5tjEhNocO2YnMWN6z/ZLB6uv8li ceNXG6tFx5EWRosph7+wWHzbso3RYvnrjewWb/d2sjtweMxuuMjisXPWXXaPBZtKPe5c28Pm cfbODkaPvi2rGAPYorhsUlJzMstSi/TtErgyVmzULujWrJj74B9bA+NfxS5GTg4JAROJvkvn GCFsMYkL99azdTFycQgJLGWUOHZlKStM0ekTa1kgEtMZJf71z2WFcHqZJE59Pw/UwsHBJqAq 8WuxPUiDiICexLxJ78AmMQv0MErsXXqVCSQhLGAq8XXyZbB1LED1/w7/ZQexeQU8JLpuHoDa JifxYc8jsDingKfE+3k7wHqFgGruHH0ItlhCYBW7xM0D11kgBglIfJt8iAXkCAkBWYlNB5gh 5khKHFxxg2UCo/ACRoZVjKKpBckFxUnpRSZ6xYm5xaV56XrJ+bmbGIGhf/rfswk7GO8dsD7E mAw0biKzlGhyPjB28kriDY3NjCxMTUyNjcwtzUgTVhLnVW+xDhQSSE8sSc1OTS1ILYovKs1J LT7EyMTBKdXA2Hz+rO8EX4c5LFWr5PS3fLmprnAmS7H+8sW5yovSpucZLff3dT3fyfo07cq6 y3dXxf3/Eta3QFD4bZTJvKn7U0U5WXLc//+Vj8tXlq19dyRtVnnxFGlJlVln3D/f2mEypzim 2M2q1Pi/+J2Ib9/SJlzU3BBsfEDgxLr7yo0JclJ7DU5vX7NyrRJLcUaioRZzUXEiAK3JUAGT AgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrLIsWRmVeSWpSXmKPExsVy+t9jQd0ck5hAg2trRS1uXP/JZvFw/U0W ixu/2lgtOo60MFpMOfyFxeLblm2MFstfb2S3eLu3k92Bw2N2w0UWj52z7rJ7LNhU6nHn2h42 j7N3djB69G1ZxRjAFtXAaJORmpiSWqSQmpecn5KZl26r5B0c7xxvamZgqGtoaWGupJCXmJtq q+TiE6DrlpkDdJGSQlliTilQKCCxuFhJ3w7ThNAQN10LmMYIXd+QILgeIwM0kLCGMWPFRu2C bs2KuQ/+sTUw/lXsYuTkkBAwkTh9Yi0LhC0mceHeerYuRi4OIYHpjBL/+ueyQji9TBKnvp8H ynBwsAmoSvxabA/SICKgJzFv0juwBmaBHkaJvUuvMoEkhAVMJb5OvswIYrMA1f87/JcdxOYV 8JDounmAFWKbnMSHPY/A4pwCnhLv5+0A6xUCqrlz9CHrBEbeBYwMqxhFUwuSC4qT0nMN9YoT c4tL89L1kvNzNzGCI+uZ1A7GlQ0WhxgFOBiVeHhPfIkKFGJNLCuuzD3EKMHBrCTCy3k8OlCI NyWxsiq1KD++qDQntfgQYzLQVROZpUST84FRn1cSb2hsYm5qbGppYmFiZkmasJI474FW60Ah gfTEktTs1NSC1CKYLUwcnFINjFHn0uP/d815VWRwo/xc2AmfRWsKFh+vTpmp8Df/1crs7nVJ qdffNX3Svn6407nkhM3mwpgFXGbH/qZtXqD5oiY1uCRccou3gtPZ6Z3FcdvPsG8V2OLxz03w 1erdb+rm/NP/Ybg952/3i48bu/5uV9n3XYdPQShA/CR7U9irqylcZl6G7Nnq8kosxRmJhlrM RcWJACyG1LnwAgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-Gm-Message-State: ALoCoQk9e8BwMLthn6ZSvNs6g1X7UC+CWdVh7m+pX+bMRjvvZZw1Ju5iY5ku+8u1f0rCwbJqlXHv X-Original-Sender: patch@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.172 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This patch adds support for EMMC booting on SMDK5250. Signed-off-by: Amar --- Changes since V1: 1)Updated spl_boot.c file to maintain irom pointer table instead of using the #define values defined in header file. Changes since V2: 1)Updation of commit message and resubmition of proper patch set. Changes since V3: No change. Changes since V4: 1)The function get_irom_func(int index) has been added to avoid type casting at many places. 2)The changes to file arch/arm/include/asm/arch-exynos/clk.h are included in this patch file. Changes since V5: No change. Changes since V6: No change. Changes since V7: 1)The macros FSYS1_MMC0_DIV_MASK and FSYS1_MMC0_DIV_VAL are made local to file clock_init.c. board/samsung/smdk5250/clock_init.c | 18 +++++++++++++ board/samsung/smdk5250/clock_init.h | 5 ++++ board/samsung/smdk5250/spl_boot.c | 52 ++++++++++++++++++++++++++++++++----- 3 files changed, 69 insertions(+), 6 deletions(-) diff --git a/board/samsung/smdk5250/clock_init.c b/board/samsung/smdk5250/clock_init.c index 5b9e82f..b288e66 100644 --- a/board/samsung/smdk5250/clock_init.c +++ b/board/samsung/smdk5250/clock_init.c @@ -28,10 +28,14 @@ #include #include #include +#include #include "clock_init.h" #include "setup.h" +#define FSYS1_MMC0_DIV_MASK 0xff0f +#define FSYS1_MMC0_DIV_VAL 0x0701 + DECLARE_GLOBAL_DATA_PTR; struct arm_clk_ratios arm_clk_ratios[] = { @@ -664,3 +668,17 @@ void clock_init_dp_clock(void) /* We run DP at 267 Mhz */ setbits_le32(&clk->div_disp1_0, CLK_DIV_DISP1_0_FIMD1); } + +/* + * Set clock divisor value for booting from EMMC. + * Set DWMMC channel-0 clk div to operate mmc0 device at 50MHz. + */ +void emmc_boot_clk_div_set(void) +{ + struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE; + unsigned int div_mmc; + + div_mmc = readl((unsigned int) &clk->div_fsys1) & ~FSYS1_MMC0_DIV_MASK; + div_mmc |= FSYS1_MMC0_DIV_VAL; + writel(div_mmc, (unsigned int) &clk->div_fsys1); +} diff --git a/board/samsung/smdk5250/clock_init.h b/board/samsung/smdk5250/clock_init.h index f751bcb..20a1d47 100644 --- a/board/samsung/smdk5250/clock_init.h +++ b/board/samsung/smdk5250/clock_init.h @@ -146,4 +146,9 @@ struct mem_timings *clock_get_mem_timings(void); * Initialize clock for the device */ void system_clock_init(void); + +/* + * Set clock divisor value for booting from EMMC. + */ +void emmc_boot_clk_div_set(void); #endif diff --git a/board/samsung/smdk5250/spl_boot.c b/board/samsung/smdk5250/spl_boot.c index d8f3c1e..fa2c0b2 100644 --- a/board/samsung/smdk5250/spl_boot.c +++ b/board/samsung/smdk5250/spl_boot.c @@ -23,15 +23,42 @@ #include #include +#include +#include +#include + +#include "clock_init.h" + +/* Index into irom ptr table */ +enum index { + MMC_INDEX, + EMMC44_INDEX, + EMMC44_END_INDEX, + SPI_INDEX, +}; + +/* IROM Function Pointers Table */ +u32 irom_ptr_table[] = { + [MMC_INDEX] = 0x02020030, /* iROM Function Pointer-SDMMC boot */ + [EMMC44_INDEX] = 0x02020044, /* iROM Function Pointer-EMMC4.4 boot*/ + [EMMC44_END_INDEX] = 0x02020048,/* iROM Function Pointer + -EMMC4.4 end boot operation */ + [SPI_INDEX] = 0x02020058, /* iROM Function Pointer-SPI boot */ + }; + enum boot_mode { BOOT_MODE_MMC = 4, BOOT_MODE_SERIAL = 20, + BOOT_MODE_EMMC = 8, /* EMMC4.4 */ /* Boot based on Operating Mode pin settings */ BOOT_MODE_OM = 32, BOOT_MODE_USB, /* Boot using USB download */ }; - typedef u32 (*spi_copy_func_t)(u32 offset, u32 nblock, u32 dst); +void *get_irom_func(int index) +{ + return (void *)*(u32 *)irom_ptr_table[index]; +} /* * Copy U-boot from mmc to RAM: @@ -40,23 +67,36 @@ enum boot_mode { */ void copy_uboot_to_ram(void) { - spi_copy_func_t spi_copy; enum boot_mode bootmode; - u32 (*copy_bl2)(u32, u32, u32); - + u32 (*spi_copy)(u32 offset, u32 nblock, u32 dst); + u32 (*copy_bl2)(u32 offset, u32 nblock, u32 dst); + u32 (*copy_bl2_from_emmc)(u32 nblock, u32 dst); + void (*end_bootop_from_emmc)(void); + /* read Operation Mode ststus register to find the bootmode */ bootmode = readl(EXYNOS5_POWER_BASE) & OM_STAT; switch (bootmode) { case BOOT_MODE_SERIAL: - spi_copy = *(spi_copy_func_t *)EXYNOS_COPY_SPI_FNPTR_ADDR; + spi_copy = get_irom_func(SPI_INDEX); spi_copy(SPI_FLASH_UBOOT_POS, CONFIG_BL2_SIZE, CONFIG_SYS_TEXT_BASE); break; case BOOT_MODE_MMC: - copy_bl2 = (void *) *(u32 *)COPY_BL2_FNPTR_ADDR; + copy_bl2 = get_irom_func(MMC_INDEX); copy_bl2(BL2_START_OFFSET, BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE); break; + case BOOT_MODE_EMMC: + /* Set the FSYS1 clock divisor value for EMMC boot */ + emmc_boot_clk_div_set(); + + copy_bl2_from_emmc = get_irom_func(EMMC44_INDEX); + end_bootop_from_emmc = get_irom_func(EMMC44_END_INDEX); + + copy_bl2_from_emmc(BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE); + end_bootop_from_emmc(); + break; + default: break; }