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[203.254.224.34]) by mx.google.com with ESMTP id b2si11063560pav.259.2013.02.14.21.38.51; Thu, 14 Feb 2013 21:38:51 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.34 as permitted sender) client-ip=203.254.224.34; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.34 as permitted sender) smtp.mail=rajeshwari.s@samsung.com Received: from epcpsbgr3.samsung.com (u143.gpu120.samsung.co.kr [203.254.230.143]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MI80046EYCPVMC0@mailout4.samsung.com>; Fri, 15 Feb 2013 14:38:50 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.122]) by epcpsbgr3.samsung.com (EPCPMTA) with SMTP id 9A.83.03448.AE9CD115; Fri, 15 Feb 2013 14:38:50 +0900 (KST) X-AuditID: cbfee68f-b7f656d000000d78-17-511dc9eaa76d Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 3A.29.03880.AE9CD115; Fri, 15 Feb 2013 14:38:50 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MI8007CCYCJCBN0@mmp1.samsung.com>; Fri, 15 Feb 2013 14:38:50 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, sjg@chromium.org, mk7.kang@samsung.com, chander.kashyap@linaro.org Subject: [PATCH 1/6 V4] EXYNOS5: Add function to enable XXTI clock source Date: Fri, 15 Feb 2013 11:16:11 +0530 Message-id: <1360907176-18802-2-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1360907176-18802-1-git-send-email-rajeshwari.s@samsung.com> References: <1360907176-18802-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrFLMWRmVeSWpSXmKPExsWyRsSkSvfVSdlAg21vNCwerr/JYjHl8BcW ByaPO9f2sAUwRnHZpKTmZJalFunbJXBlvL2/kLngNV/FqWXXWBsYu3m6GDk5JARMJF6+XcQC YYtJXLi3nq2LkYtDSGApo8T2XTOYYIpW7LjFDpFYxCjRdnMKE4QzkUmifcEWRpAqNgEjia0n p4HZIgISEr/6r4LZzAIxEq/3/wAay8EhLOApsf2YFEiYRUBVYuL3T+wgNq+Ah8S2f79ZIZYp SByb+hXM5gQqf3HxC9h1QkA1b47fBLtOQuA2m8SnK/PZIAYJSHybfIgFZL6EgKzEpgPMEHMk JQ6uuMEygVF4ASPDKkbR1ILkguKk9CJjveLE3OLSvHS95PzcTYzAcDz971n/Dsa7B6wPMSYD jZvILCWanA8M57ySeENjE3NTY1MzI0tLS1PShJXEeeUvyQQKCaQnlqRmp6YWpBbFF5XmpBYf YmTi4JRqYAycfi/fIrjI5+K3jT+X5ayTZ8tb0/Vixm6LVwK5HR8CQrR4ParOlB1aN3udyPVJ EorTDLXO/L16r2i29A0B50+2hbdFWffuVL9Ve1TuW4HqCb6V5eve3prOJcmzO37Xs/csiU2r Va6ILPj871wwg0XXBk+d2uP3T2ZIaWtzC7+d5x62an7TkZNKLMUZiYZazEXFiQCm6TblXQIA AA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrOIsWRmVeSWpSXmKPExsVy+t9jAd1XJ2UDDfauULB4uP4mi8WUw19Y HJg87lzbwxbAGNXAaJORmpiSWqSQmpecn5KZl26r5B0c7xxvamZgqGtoaWGupJCXmJtqq+Ti E6DrlpkDNFtJoSwxpxQoFJBYXKykb4dpQmiIm64FTGOErm9IEFyPkQEaSFjDmPH2/kLmgtd8 FaeWXWNtYOzm6WLk5JAQMJFYseMWO4QtJnHh3nq2LkYuDiGBRYwSbTenMEE4E5kk2hdsYQSp YhMwkth6chqYLSIgIfGr/yqYzSwQI/F6/w+gbg4OYQFPie3HpEDCLAKqEhO/fwJbwCvgIbHt 329WiGUKEsemfgWzOYHKX1z8wgJiCwHVvDl+k20CI+8CRoZVjKKpBckFxUnpuUZ6xYm5xaV5 6XrJ+bmbGMHB/kx6B+OqBotDjAIcjEo8vAISsoFCrIllxZW5hxglOJiVRHjXhACFeFMSK6tS i/Lji0pzUosPMSYDXTWRWUo0OR8YiXkl8YbGJuamxqaWJhYmZpakCSuJ8zKeehIgJJCeWJKa nZpakFoEs4WJg1OqgTHh4wTT7H/qhb9rZGr5eyRyVWdcvdD3aWdkwdOuV5MnqWRyia9JjGU+ vvU7e9KF5zrMBgGupwzWO+50b+n1+BMy665XeEjNwzczvUseGfztuP5ctOFg7Z/CuiuOh2/M EBJR+1a3drn0Sf/pM+Sjb3zi3my/8nrnh91qLUdE0rtfp9nr+BTtuavEUpyRaKjFXFScCAD2 7gxjugIAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-Gm-Message-State: ALoCoQlLqt9v/nXyCg1rTrm3ezePsA2bNUq3v5EinFBborvPrAY7T8fLDzTugXdGCfXM34itfsW1 This patch adds funtion to enable XXTI clock source required by MAX98095 codec. Signed-off-by: Rajeshwari Shinde --- Changes in V2: - Corrected multi-line comment style Changes in V3: - None Changes in V4: - Modified XXTI clock source function as per Exynos naming convention arch/arm/cpu/armv7/exynos/power.c | 17 +++++++++++++++++ arch/arm/include/asm/arch-exynos/power.h | 11 +++++++++++ 2 files changed, 28 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/power.c b/arch/arm/cpu/armv7/exynos/power.c index 400c8bc..db7249e 100644 --- a/arch/arm/cpu/armv7/exynos/power.c +++ b/arch/arm/cpu/armv7/exynos/power.c @@ -111,3 +111,20 @@ void set_ps_hold_ctrl(void) if (cpu_is_exynos5()) exynos5_set_ps_hold_ctrl(); } + + +static void exynos5_set_xclkout(void) +{ + struct exynos5_power *power = + (struct exynos5_power *)samsung_get_base_power(); + + /* use xxti for xclk out */ + clrsetbits_le32(&power->pmu_debug, PMU_DEBUG_CLKOUT_SEL_MASK, + PMU_DEBUG_XXTI); +} + +void set_xclkout(void) +{ + if (cpu_is_exynos5()) + exynos5_set_xclkout(); +} diff --git a/arch/arm/include/asm/arch-exynos/power.h b/arch/arm/include/asm/arch-exynos/power.h index f2f73fa..5f26337 100644 --- a/arch/arm/include/asm/arch-exynos/power.h +++ b/arch/arm/include/asm/arch-exynos/power.h @@ -873,4 +873,15 @@ void set_dp_phy_ctrl(unsigned int enable); * (e.g. power button). */ void set_ps_hold_ctrl(void); + +/* PMU_DEBUG bits [12:8] = 0x1000 selects XXTI clock source */ +#define PMU_DEBUG_XXTI 0x1000 +/* Mask bit[12:8] for xxti clock selection */ +#define PMU_DEBUG_CLKOUT_SEL_MASK 0x1f00 + +/* + * Pmu debug is used for xclkout, enable xclkout with + * source as XXTI + */ +void set_xclkout(void); #endif