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[203.254.224.34]) by mx.google.com with ESMTP id qu6si23357084pbc.225.2013.01.24.01.35.52; Thu, 24 Jan 2013 01:35:52 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.34 as permitted sender) client-ip=203.254.224.34; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.34 as permitted sender) smtp.mail=rajeshwari.s@samsung.com Received: from epcpsbgm1.samsung.com (epcpsbgm1 [203.254.230.26]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MH4002VMINOK8W0@mailout4.samsung.com>; Thu, 24 Jan 2013 18:35:51 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.123]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 6A.02.03918.77001015; Thu, 24 Jan 2013 18:35:51 +0900 (KST) X-AuditID: cbfee61a-b7f7d6d000000f4e-9a-510100779207 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 78.02.03918.77001015; Thu, 24 Jan 2013 18:35:51 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MH400JQFINGXJ10@mmp2.samsung.com>; Thu, 24 Jan 2013 18:35:51 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, alim.akhtar@samsung.com, sjg@chromium.org, mk7.kang@samsung.com, chander.kashyap@linaro.org Subject: [PATCH 1/7 V2] EXYNOS5: Add function to enable XXTI clock source Date: Thu, 24 Jan 2013 15:13:34 +0530 Message-id: <1359020620-11873-2-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1359020620-11873-1-git-send-email-rajeshwari.s@samsung.com> References: <1359020620-11873-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrCLMWRmVeSWpSXmKPExsWyRsSkWrecgTHQoPO0jMXD9TdZLKYc/sLi wORx59oetgDGKC6blNSczLLUIn27BK6MBc3SBZt5K3Y2TmZvYOzg7mLk5JAQMJHYdu8uI4Qt JnHh3nq2LkYuDiGBpYwS03oms8IU7Tv7lQUiMZ1R4sqHP0wgCSGBiUwSDReTQGw2ASOJrSen gU0SEZCQ+NV/Fcjm4GAWKJWYMjEPxBQW8JSY8CwLpIJFQFXi38vHbCA2r4CHxLftj6FWKUgc m/qVFaScE6h8aqMsxCIPiZc39oKdJiFwm01i/ZeVbBBzBCS+TT7EAlIvISArsekAM8QYSYmD K26wTGAUXsDIsIpRNLUguaA4KT3XUK84Mbe4NC9dLzk/dxMjMAxP/3smtYNxZYPFIUYBDkYl Hl4FVYZAIdbEsuLK3EOMEhzMSiK8sS+BQrwpiZVVqUX58UWlOanFhxiTgZZPZJYSTc4Hxkhe SbyhsYm5qbGppZGRmakpacJK4ryMp54ECAmkJ5akZqemFqQWwWxh4uCUamBU3PT169xfOes+ PrqQPrHz1iOdbl6zufccMhWk8sXWThdw67Vh7TxYIe0Wu/n3w7dXvkhyXWNdxGE/e0dz5uEd /h6BvydO47KRyfTKTJzvO2NSx6LaksXXNiS1Tc5kv7HR+xbf3gtic7n+f5o86+gT4flnFaZw eq/1bFxwiX1T3Z1Xa0Vmrbi5W4mlOCPRUIu5qDgRAOyLUyyHAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrMIsWRmVeSWpSXmKPExsVy+t9jQd1yBsZAg9OruC0err/JYjHl8BcW ByaPO9f2sAUwRjUw2mSkJqakFimk5iXnp2TmpdsqeQfHO8ebmhkY6hpaWpgrKeQl5qbaKrn4 BOi6ZeYAzVZSKEvMKQUKBSQWFyvp22GaEBripmsB0xih6xsSBNdjZIAGEtYwZixoli7YzFux s3EyewNjB3cXIyeHhICJxL6zX1kgbDGJC/fWs3UxcnEICUxnlLjy4Q8TSEJIYCKTRMPFJBCb TcBIYuvJaYwgtoiAhMSv/qtANgcHs0CpxJSJeSCmsICnxIRnWSAVLAKqEv9ePmYDsXkFPCS+ bX/MCrFKQeLY1K+sIOWcQOVTG2UhFnlIvLyxl20CI+8CRoZVjKKpBckFxUnpuYZ6xYm5xaV5 6XrJ+bmbGMFB/kxqB+PKBotDjAIcjEo8vAqqDIFCrIllxZW5hxglOJiVRHhjXwKFeFMSK6tS i/Lji0pzUosPMSYDHTWRWUo0OR8YgXkl8YbGJuamxqaWJhYmZpakCSuJ8zKeehIgJJCeWJKa nZpakFoEs4WJg1OqgTFAgqvsR+TNrLXKj1bEBNz8zz9RRGzf19I3ybMYNkV+X5vjZB6i5n9r R8ThgoXmb+JtPk/juPVPvPi6+v38q6tvCHpwvfefEHxFftGHD+XcWdsC2PfzVPTvP1Bc5STW qblk2/azTyZ7HxUJ01oqu8OHc7KccoeQuYh8k7zyJL4/n7e5Ze98eE+JpTgj0VCLuag4EQCd 0+/utgIAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-Gm-Message-State: ALoCoQmNoTk8ks/wJkEKfzLS3tm64fDv34UHG1o/+vDeFMESXK/PT+B2UOU88NKOQLLwYj36Rt9p This patch adds funtion to enable XXTI clock source required by MAX98095 codec. Signed-off-by: Rajeshwari Shinde Acked-by: Simon Glass --- Changes in V2: - Corrected multi-line comment style arch/arm/cpu/armv7/exynos/power.c | 11 +++++++++++ arch/arm/include/asm/arch-exynos/power.h | 11 +++++++++++ 2 files changed, 22 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/power.c b/arch/arm/cpu/armv7/exynos/power.c index 8572cfd..8de30c1 100644 --- a/arch/arm/cpu/armv7/exynos/power.c +++ b/arch/arm/cpu/armv7/exynos/power.c @@ -105,3 +105,14 @@ void power_ps_hold_setup(void) setbits_le32(&power->ps_hold_control, EXYNOS_PS_HOLD_CONTROL_DATA_HIGH); } + + +void power_enable_xclkout(void) +{ + struct exynos5_power *power = + (struct exynos5_power *)samsung_get_base_power(); + + /* use xxti for xclk out */ + clrsetbits_le32(&power->pmu_debug, PMU_DEBUG_CLKOUT_SEL_MASK, + PMU_DEBUG_XXTI); +} diff --git a/arch/arm/include/asm/arch-exynos/power.h b/arch/arm/include/asm/arch-exynos/power.h index 85e2cd9..09343d7 100644 --- a/arch/arm/include/asm/arch-exynos/power.h +++ b/arch/arm/include/asm/arch-exynos/power.h @@ -872,4 +872,15 @@ void set_dp_phy_ctrl(unsigned int enable); * (e.g. power button). */ void power_ps_hold_setup(void); + +/* PMU_DEBUG bits [12:8] = 0x1000 selects XXTI clock source */ +#define PMU_DEBUG_XXTI 0x1000 +/* Mask bit[12:8] for xxti clock selection */ +#define PMU_DEBUG_CLKOUT_SEL_MASK 0x1f00 + +/* + * Pmu debug is used for xclkout, enable xclkout with + * source as XXTI + */ +void power_enable_xclkout(void); #endif