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[203.254.224.34]) by mx.google.com with ESMTP id uq10si13309830pbc.317.2013.01.21.02.46.23; Mon, 21 Jan 2013 02:46:23 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.34 as permitted sender) client-ip=203.254.224.34; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.34 as permitted sender) smtp.mail=rajeshwari.s@samsung.com Received: from epcpsbgm2.samsung.com (epcpsbgm2 [203.254.230.27]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MGZ00DCF1W0GM20@mailout4.samsung.com>; Mon, 21 Jan 2013 19:46:22 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.123]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 03.82.03880.E7C1DF05; Mon, 21 Jan 2013 19:46:22 +0900 (KST) X-AuditID: cbfee61b-b7fb06d000000f28-d8-50fd1c7e1f0c Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 42.82.03880.D7C1DF05; Mon, 21 Jan 2013 19:46:22 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MGZ009CX1UTT630@mmp1.samsung.com>; Mon, 21 Jan 2013 19:46:21 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, sjg@chromium.org, mk7.kang@samsung.com, chander.kashyap@linaro.org Subject: [PATCH 1/7] EXYNOS5: Add function to enable XXTI clock source Date: Mon, 21 Jan 2013 16:22:33 +0530 Message-id: <1358765559-32709-2-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1358765559-32709-1-git-send-email-rajeshwari.s@samsung.com> References: <1358765559-32709-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrOLMWRmVeSWpSXmKPExsWyRsSkWrdO5m+AwcIfvBYP199ksZhy+AuL A5PHnWt72AIYo7hsUlJzMstSi/TtErgyrq2bxljwhadi4pWVbA2Mt7i6GDk5JARMJN7+ucIE YYtJXLi3ng3EFhJYyiixbYMLTM2XhzdZuhi5gOKLGCXWflnGCuFMZJK4N+MNWAebgJHE1pPT GEFsEQEJiV/9V8FsZoEYidf7f4DVCAu4SXS13gGzWQRUJTbc+MXexcjBwSvgIfGz0x5imYLE salfWUFsTgFPiRsHNrFAHOQh8WfjSmaQvRIC99kkJnVPZIeYIyDxbfIhFpA5EgKyEpsOMEPM kZQ4uOIGywRG4QWMDKsYRVMLkguKk9JzjfSKE3OLS/PS9ZLzczcxAoPx9L9n0jsYVzVYHGIU 4GBU4uFN6PsTIMSaWFZcmXuIUYKDWUmE9+cMoBBvSmJlVWpRfnxRaU5q8SHGZKDlE5mlRJPz gZGSVxJvaGxibmpsamlkZGZqSpqwkjgv46knAUIC6YklqdmpqQWpRTBbmDg4pRoYw6t8jN+2 BJ8N+ieTyhmwrN0lW1nvZmb/1qxNk35sUD+iuTf1kPaTAEWXjLU9dkWZn8+lHpP1XHngZvjv LS7eXFVXLgifPyd1bwLHTKV7grNnKYTWPW2YncMy/9DVidK8m2Z83n3gscC6pwelhNR3L+G4 HvfWreqLY3PCa9YL6VJS31aEn6mSU2Ipzkg01GIuKk4EAPyB6OeKAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrOIsWRmVeSWpSXmKPExsVy+t9jAd06mb8BBg+us1o8XH+TxWLK4S8s Dkwed67tYQtgjGpgtMlITUxJLVJIzUvOT8nMS7dV8g6Od443NTMw1DW0tDBXUshLzE21VXLx CdB1y8wBmq2kUJaYUwoUCkgsLlbSt8M0ITTETdcCpjFC1zckCK7HyAANJKxhzLi2bhpjwRee iolXVrI1MN7i6mLk5JAQMJH48vAmC4QtJnHh3nq2LkYuDiGBRYwSa78sY4VwJjJJ3Jvxhg2k ik3ASGLryWmMILaIgITEr/6rYDazQIzE6/0/wGqEBdwkulrvgNksAqoSG278Yu9i5ODgFfCQ +NlpD7FMQeLY1K+sIDangKfEjQObwI4QAir5s3El8wRG3gWMDKsYRVMLkguKk9JzjfSKE3OL S/PS9ZLzczcxgoP9mfQOxlUNFocYBTgYlXh4E/r+BAixJpYVV+YeYpTgYFYS4f05AyjEm5JY WZValB9fVJqTWnyIMRnoqInMUqLJ+cBIzCuJNzQ2MTc1NrU0sTAxsyRNWEmcl/HUkwAhgfTE ktTs1NSC1CKYLUwcnFINjNmRP+IYina94d5Z9TF6dfumu8tmPlBR+H3hZUh70q0VPwzV2QMu rbt6f/Nqd9l3MiZzP89gXCrO7iFyIcS8zWdNicyt7gNM1gocDTY1p/pveX8z3nh00qPjtgfX rG9tuPN179zUh1JrUi4KBPZs4K8ze/MiaPeUd36Gd5MjOhv3zvU238Mz00qJpTgj0VCLuag4 EQCIa80zugIAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-Gm-Message-State: ALoCoQnEZ3kSIWZYhcp+Vc4cVWGVIkBc6VargNP3CZfHJX/fZfIt3d0XXvLRerMm5NFSNzHgeWBd This patch adds funtion to enable XXTI clock source required by MAX98095 codec. Signed-off-by: Rajeshwari Shinde --- arch/arm/cpu/armv7/exynos/power.c | 11 +++++++++++ arch/arm/include/asm/arch-exynos/power.h | 10 ++++++++++ 2 files changed, 21 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/power.c b/arch/arm/cpu/armv7/exynos/power.c index 8572cfd..8de30c1 100644 --- a/arch/arm/cpu/armv7/exynos/power.c +++ b/arch/arm/cpu/armv7/exynos/power.c @@ -105,3 +105,14 @@ void power_ps_hold_setup(void) setbits_le32(&power->ps_hold_control, EXYNOS_PS_HOLD_CONTROL_DATA_HIGH); } + + +void power_enable_xclkout(void) +{ + struct exynos5_power *power = + (struct exynos5_power *)samsung_get_base_power(); + + /* use xxti for xclk out */ + clrsetbits_le32(&power->pmu_debug, PMU_DEBUG_CLKOUT_SEL_MASK, + PMU_DEBUG_XXTI); +} diff --git a/arch/arm/include/asm/arch-exynos/power.h b/arch/arm/include/asm/arch-exynos/power.h index 85e2cd9..f0eab16 100644 --- a/arch/arm/include/asm/arch-exynos/power.h +++ b/arch/arm/include/asm/arch-exynos/power.h @@ -872,4 +872,14 @@ void set_dp_phy_ctrl(unsigned int enable); * (e.g. power button). */ void power_ps_hold_setup(void); + +/* PMU_DEBUG bits [12:8] = 0x1000 selects XXTI + * clock source */ +#define PMU_DEBUG_XXTI 0x1000 +/* Mask bit[12:8] for xxti clock selection */ +#define PMU_DEBUG_CLKOUT_SEL_MASK 0x1f00 + +/* pmu debug is used for xclkout, enable xclkout with + * source as XXTI */ +void power_enable_xclkout(void); #endif